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We were (somehow) getting the wrong branch opcode for setcc float instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17925 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1176,8 +1176,8 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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unsigned Column = 0;
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if (Ty->isSigned()) ++Column;
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if (Ty->isFloatingPoint()) ++Column;
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if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
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if (Ty->isFloatingPoint()) Column = 2;
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static unsigned OpcodeTab[3*6] = {
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// LLVM SparcV8
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// unsigned signed fp
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@ -1176,8 +1176,8 @@ void V8ISel::visitSetCondInst(SetCondInst &I) {
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case Instruction::SetGE: BranchIdx = 5; break;
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}
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unsigned Column = 0;
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if (Ty->isSigned()) ++Column;
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if (Ty->isFloatingPoint()) ++Column;
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if (Ty->isSigned() && !Ty->isFloatingPoint()) Column = 1;
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if (Ty->isFloatingPoint()) Column = 2;
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static unsigned OpcodeTab[3*6] = {
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// LLVM SparcV8
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// unsigned signed fp
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