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https://github.com/c64scene-ar/llvm-6502.git
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R600: Use i24 optimized path for SREM
v2: add tests
rename LowerSDIV24 to LowerSDIVREM24
handle the rem part in this function
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215460 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jan Vesely
parent
693defb6ea
commit
b40562c0ec
@ -250,7 +250,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
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for (MVT VT : ScalarIntVTs) {
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::SDIV, VT, Custom);
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setOperationAction(ISD::SDIV, VT, Expand);
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// GPU does not have divrem function for signed or unsigned.
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setOperationAction(ISD::SDIVREM, VT, Custom);
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@ -1390,7 +1390,7 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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// This is a shortcut for integer division because we have fast i32<->f32
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// conversions, and fast f32 reciprocal instructions. The fractional part of a
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// float is enough to accurately represent up to a 24-bit integer.
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SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
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SDValue AMDGPUTargetLowering::LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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@ -1463,7 +1463,17 @@ SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
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// dst = iq + jq;
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iq = DAG.getSExtOrTrunc(iq, DL, VT);
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return DAG.getNode(ISD::ADD, DL, VT, iq, jq);
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SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
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SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
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Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
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SDValue Res[2] = {
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Div,
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Rem
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};
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return DAG.getMergeValues(Res, DL);
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}
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SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
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@ -1544,7 +1554,7 @@ SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
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// TODO: We technically could do this for i64, but shouldn't that just be
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// handled by something generally reducing 64-bit division on 32-bit
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// values to 32-bit?
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return LowerSDIV24(Op, DAG);
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// return LowerSDIV24(Op, DAG);
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}
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return LowerSDIV32(Op, DAG);
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@ -1740,12 +1750,22 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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SDValue Zero = DAG.getConstant(0, VT);
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SDValue NegOne = DAG.getConstant(-1, VT);
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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if (VT == MVT::i32) {
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if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
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DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
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// TODO: We technically could do this for i64, but shouldn't that just be
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// handled by something generally reducing 64-bit division on 32-bit
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// values to 32-bit?
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return LowerSDIVREM24(Op, DAG);
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}
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}
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SDValue Zero = DAG.getConstant(0, VT);
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SDValue NegOne = DAG.getConstant(-1, VT);
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SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
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SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
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SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
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@ -44,7 +44,6 @@ private:
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/// \returns The resulting chain.
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SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
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@ -89,6 +88,7 @@ protected:
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIVREM24(SDValue Op, SelectionDAG &DAG) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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@ -118,3 +118,121 @@ define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in)
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @srem24_i8
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = srem i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @srem24_i16
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = srem i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: @srem24_i32
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @srem25_i32
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_srem24_i32_1
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_srem24_i32_2
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_srem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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