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https://github.com/c64scene-ar/llvm-6502.git
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[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
4cc117883d
commit
b4691b495d
@ -1076,6 +1076,13 @@ class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass Itinerary = itin;
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}
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class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
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RegisterClass RCD, RegisterClass RCWS> :
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MipsPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4:$n),
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[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4:$n))]> {
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bit usesCustomInserter = 1;
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}
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class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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SplatComplexPattern SplatImm, RegisterClass RCWD,
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RegisterClass RCWS = RCWD,
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@ -1581,6 +1588,11 @@ class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
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class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
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GPR32, MSA128W>;
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class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
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MSA128W>;
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class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
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MSA128D>;
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class CTCMSA_DESC {
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dag OutOperandList = (outs);
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dag InOperandList = (ins MSACtrl:$cd, GPR32:$rs);
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@ -2579,6 +2591,9 @@ def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
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def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
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def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
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def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
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def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
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def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
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def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
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@ -827,6 +827,10 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
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case Mips::SZ_V_PSEUDO:
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return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
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case Mips::COPY_FW_PSEUDO:
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return emitCOPY_FW(MI, BB);
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case Mips::COPY_FD_PSEUDO:
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return emitCOPY_FD(MI, BB);
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}
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}
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@ -1662,10 +1666,19 @@ lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT ResTy = Op->getValueType(0);
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SDValue Op0 = Op->getOperand(0);
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SDValue Op1 = Op->getOperand(1);
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EVT EltTy = Op0->getValueType(0).getVectorElementType();
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return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
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DAG.getValueType(EltTy));
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EVT VecTy = Op0->getValueType(0);
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if (!VecTy.is128BitVector())
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return SDValue();
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if (ResTy.isInteger()) {
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SDValue Op1 = Op->getOperand(1);
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EVT EltTy = VecTy.getVectorElementType();
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return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
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DAG.getValueType(EltTy));
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}
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return Op;
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}
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static bool isConstantOrUndef(const SDValue Op) {
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@ -2236,3 +2249,69 @@ emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return Sink;
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}
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// Emit the COPY_FW pseudo instruction.
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//
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// copy_fw_pseudo $fd, $ws, n
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// =>
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// copy_u_w $rt, $ws, $n
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// mtc1 $rt, $fd
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//
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// When n is zero, the equivalent operation can be performed with (potentially)
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// zero instructions due to register overlaps. This optimization is never valid
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// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
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MachineBasicBlock * MipsSETargetLowering::
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emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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DebugLoc DL = MI->getDebugLoc();
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unsigned Fd = MI->getOperand(0).getReg();
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unsigned Ws = MI->getOperand(1).getReg();
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unsigned Lane = MI->getOperand(2).getImm();
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if (Lane == 0)
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
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else {
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unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1);
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
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}
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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// Emit the COPY_FD pseudo instruction.
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//
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// copy_fd_pseudo $fd, $ws, n
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// =>
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// splati.d $wt, $ws, $n
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// copy $fd, $wt:sub_64
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//
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// When n is zero, the equivalent operation can be performed with (potentially)
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// zero instructions due to register overlaps. This optimization is always
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// valid because FR=1 mode which is the only supported mode in MSA.
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MachineBasicBlock * MipsSETargetLowering::
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emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
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assert(Subtarget->isFP64bit());
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
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unsigned Fd = MI->getOperand(0).getReg();
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unsigned Ws = MI->getOperand(1).getReg();
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unsigned Lane = MI->getOperand(2).getImm() * 2;
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DebugLoc DL = MI->getDebugLoc();
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if (Lane == 0)
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
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else {
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unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
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}
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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@ -84,6 +84,12 @@ namespace llvm {
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MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned BranchOp) const;
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/// \brief Emit the COPY_FW pseudo instruction
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MachineBasicBlock *emitCOPY_FW(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// \brief Emit the COPY_FD pseudo instruction
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MachineBasicBlock *emitCOPY_FD(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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@ -55,3 +55,83 @@ define void @const_v2f64() nounwind {
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ret void
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; MIPS32: .size const_v2f64
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}
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define float @extract_v4f32() nounwind {
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; MIPS32: extract_v4f32:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_lo
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; MIPS32-DAG: splati.w $w0, [[R1]][1]
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ret float %3
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; MIPS32: .size extract_v4f32
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}
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define float @extract_v4f32_elt0() nounwind {
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; MIPS32: extract_v4f32_elt0:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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ret float %3
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; MIPS32: .size extract_v4f32_elt0
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}
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define double @extract_v2f64() nounwind {
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; MIPS32: extract_v2f64:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_64
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; MIPS32-DAG: splati.d $w0, [[R1]][1]
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64
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}
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define double @extract_v2f64_elt0() nounwind {
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; MIPS32: extract_v2f64_elt0:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64_elt0
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}
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141
test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
Normal file
141
test/CodeGen/Mips/msa/llvm-stress-s997348632.ll
Normal file
@ -0,0 +1,141 @@
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; RUN: llc -march=mips < %s
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
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; This test originally failed to select instructions for extract_vector_elt for
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; v2f64 on MSA.
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; It should at least successfully build.
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define void @autogen_SD997348632(i8*, i32*, i64*, i32, i64, i8) {
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BB:
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%A4 = alloca <2 x i32>
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%A3 = alloca <16 x i16>
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%A2 = alloca <4 x i1>
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%A1 = alloca <4 x i16>
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%A = alloca <2 x i32>
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%L = load i8* %0
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store i8 %L, i8* %0
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%E = extractelement <4 x i32> zeroinitializer, i32 0
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%Shuff = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 1, i32 3, i32 5>
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%I = insertelement <2 x i1> zeroinitializer, i1 false, i32 1
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%FC = sitofp <4 x i32> zeroinitializer to <4 x double>
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%Sl = select i1 false, <4 x i64> %Shuff, <4 x i64> %Shuff
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%L5 = load i8* %0
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store i8 %5, i8* %0
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%E6 = extractelement <1 x i16> zeroinitializer, i32 0
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%Shuff7 = shufflevector <2 x i1> %I, <2 x i1> %I, <2 x i32> <i32 1, i32 undef>
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%I8 = insertelement <1 x i16> zeroinitializer, i16 0, i32 0
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%B = xor i32 376034, %3
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%FC9 = fptoui float 0x406DB70180000000 to i64
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%Sl10 = select i1 false, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%Cmp = icmp ult <4 x i64> zeroinitializer, zeroinitializer
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%L11 = load i8* %0
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store i8 %L, i8* %0
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%E12 = extractelement <4 x i64> zeroinitializer, i32 2
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%Shuff13 = shufflevector <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> <i32 5, i32 7, i32 undef, i32 3>
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%I14 = insertelement <8 x i32> zeroinitializer, i32 -1, i32 7
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%B15 = fdiv <4 x double> %FC, %FC
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%Tr = trunc i32 376034 to i16
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%Sl16 = select i1 false, <8 x i32> %Sl10, <8 x i32> zeroinitializer
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%Cmp17 = icmp uge i32 233658, %E
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br label %CF
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CF: ; preds = %CF, %CF79, %CF84, %BB
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%L18 = load i8* %0
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store i8 %L, i8* %0
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%E19 = extractelement <4 x i64> %Sl, i32 3
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%Shuff20 = shufflevector <2 x i1> %Shuff7, <2 x i1> %I, <2 x i32> <i32 2, i32 0>
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%I21 = insertelement <4 x i64> zeroinitializer, i64 %FC9, i32 0
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%B22 = xor <8 x i32> %I14, %I14
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%Tr23 = trunc i16 0 to i8
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%Sl24 = select i1 false, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> zeroinitializer
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%Cmp25 = icmp eq i1 false, false
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br i1 %Cmp25, label %CF, label %CF79
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CF79: ; preds = %CF
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%L26 = load i8* %0
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store i8 %L26, i8* %0
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%E27 = extractelement <1 x i16> zeroinitializer, i32 0
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%Shuff28 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11>
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%I29 = insertelement <16 x i32> %Shuff28, i32 %B, i32 15
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%B30 = fdiv float 0.000000e+00, -6.749110e+06
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%Sl31 = select i1 false, i32 %3, i32 %3
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%Cmp32 = fcmp uno float 0.000000e+00, 0x406DB70180000000
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br i1 %Cmp32, label %CF, label %CF78
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CF78: ; preds = %CF78, %CF79
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%L33 = load i8* %0
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store i8 %L, i8* %0
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%E34 = extractelement <16 x i32> %Shuff28, i32 1
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%Shuff35 = shufflevector <4 x i64> zeroinitializer, <4 x i64> %I21, <4 x i32> <i32 undef, i32 6, i32 0, i32 2>
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%I36 = insertelement <4 x double> %FC, double 0xA4A57F449CA36CC2, i32 2
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%Se = sext <4 x i1> %Cmp to <4 x i32>
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%Sl37 = select i1 %Cmp17, i32 0, i32 0
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%Cmp38 = icmp ne i32 440284, 376034
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br i1 %Cmp38, label %CF78, label %CF80
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CF80: ; preds = %CF80, %CF82, %CF78
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%L39 = load i8* %0
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store i8 %L, i8* %0
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%E40 = extractelement <2 x i1> %Shuff20, i32 1
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br i1 %E40, label %CF80, label %CF82
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CF82: ; preds = %CF80
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%Shuff41 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %Shuff20, <2 x i32> <i32 2, i32 0>
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%I42 = insertelement <2 x i1> %Shuff41, i1 false, i32 0
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%B43 = sub i32 %E, 0
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%Sl44 = select i1 %Cmp32, <16 x i32> %Shuff28, <16 x i32> %Shuff28
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%Cmp45 = icmp sgt <4 x i64> zeroinitializer, %I21
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%L46 = load i8* %0
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store i8 %L11, i8* %0
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%E47 = extractelement <8 x i32> %Sl16, i32 4
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%Shuff48 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %Shuff7, <2 x i32> <i32 undef, i32 1>
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%I49 = insertelement <2 x i1> %Shuff48, i1 %Cmp17, i32 1
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%B50 = and <8 x i32> %I14, %Sl10
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%FC51 = fptoui float -6.749110e+06 to i1
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br i1 %FC51, label %CF80, label %CF81
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CF81: ; preds = %CF81, %CF82
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%Sl52 = select i1 false, float -6.749110e+06, float 0x406DB70180000000
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%Cmp53 = icmp uge <2 x i32> <i32 -1, i32 -1>, <i32 -1, i32 -1>
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%L54 = load i8* %0
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store i8 %L5, i8* %0
|
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%E55 = extractelement <8 x i32> zeroinitializer, i32 7
|
||||
%Shuff56 = shufflevector <4 x i64> zeroinitializer, <4 x i64> zeroinitializer, <4 x i32> <i32 undef, i32 4, i32 6, i32 0>
|
||||
%I57 = insertelement <2 x i1> %Shuff7, i1 false, i32 0
|
||||
%B58 = fmul <4 x double> %FC, %FC
|
||||
%FC59 = fptoui <4 x double> %I36 to <4 x i16>
|
||||
%Sl60 = select i1 %Cmp17, <2 x i1> %I, <2 x i1> %I57
|
||||
%Cmp61 = icmp ule <8 x i32> %B50, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
|
||||
%L62 = load i8* %0
|
||||
store i8 %L33, i8* %0
|
||||
%E63 = extractelement <4 x i64> %Shuff, i32 2
|
||||
%Shuff64 = shufflevector <4 x i64> %Shuff56, <4 x i64> %Shuff56, <4 x i32> <i32 5, i32 7, i32 1, i32 undef>
|
||||
%I65 = insertelement <2 x i1> zeroinitializer, i1 false, i32 1
|
||||
%B66 = sdiv i32 %B, %E55
|
||||
%Tr67 = trunc i8 %L54 to i1
|
||||
br i1 %Tr67, label %CF81, label %CF83
|
||||
|
||||
CF83: ; preds = %CF83, %CF81
|
||||
%Sl68 = select i1 %Cmp17, i1 %Cmp25, i1 %Tr67
|
||||
br i1 %Sl68, label %CF83, label %CF84
|
||||
|
||||
CF84: ; preds = %CF83
|
||||
%Cmp69 = icmp uge i32 %E, %E34
|
||||
br i1 %Cmp69, label %CF, label %CF77
|
||||
|
||||
CF77: ; preds = %CF84
|
||||
%L70 = load i8* %0
|
||||
store i8 %L, i8* %0
|
||||
%E71 = extractelement <4 x i64> %Shuff, i32 0
|
||||
%Shuff72 = shufflevector <2 x i1> zeroinitializer, <2 x i1> %I, <2 x i32> <i32 3, i32 1>
|
||||
%I73 = insertelement <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, i32 %B66, i32 1
|
||||
%FC74 = uitofp i1 %Cmp32 to double
|
||||
%Sl75 = select i1 %FC51, i16 9704, i16 0
|
||||
%Cmp76 = icmp ugt <1 x i16> %I8, %I8
|
||||
store i8 %L39, i8* %0
|
||||
store i8 %5, i8* %0
|
||||
store i8 %Tr23, i8* %0
|
||||
store i8 %L, i8* %0
|
||||
store i8 %5, i8* %0
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user