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https://github.com/c64scene-ar/llvm-6502.git
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XCore target: addMemOperand as necessary
BuildMI instructions were not including MachineMemOperand information. This was discovered by 'SingleSource/Benchmarks/Stanford/Oscar' failing due to a FrameIndex load incorrectly being hoisted by postra-machine-licm. No other tests have been found to fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201562 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lytton
parent
9409825b57
commit
b489828264
@ -44,6 +44,21 @@ static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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// Helper structure with compare function for handling stack slots.
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namespace {
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struct StackSlotInfo {
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int FI;
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int Offset;
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unsigned Reg;
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StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){};
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};
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} // end anonymous namespace
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static bool CompareSSIOffset(const StackSlotInfo& a, const StackSlotInfo& b) {
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return a.Offset < b.Offset;
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}
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static void EmitDefCfaRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc dl,
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const TargetInstrInfo &TII,
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@ -119,55 +134,73 @@ static void IfNeededLDAWSP(MachineBasicBlock &MBB,
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/// during the emitPrologue/emitEpilogue.
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/// Registers are ordered according to their frame offset.
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/// As offsets are negative, the largest offsets will be first.
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static void GetSpillList(SmallVectorImpl<std::pair<int,unsigned> > &SpillList,
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static void GetSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
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MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
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bool fetchLR, bool fetchFP) {
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if (fetchLR) {
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int Offset = MFI->getObjectOffset(XFI->getLRSpillSlot());
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SpillList.push_back(std::pair<int,unsigned>(Offset, XCore::LR));
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SpillList.push_back(StackSlotInfo(XFI->getLRSpillSlot(),
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Offset,
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XCore::LR));
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}
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if (fetchFP) {
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int Offset = MFI->getObjectOffset(XFI->getFPSpillSlot());
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SpillList.push_back(std::pair<int,unsigned>(Offset, FramePtr));
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SpillList.push_back(StackSlotInfo(XFI->getFPSpillSlot(),
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Offset,
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FramePtr));
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}
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std::sort(SpillList.begin(), SpillList.end());
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std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
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}
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/// Creates an ordered list of EH info register 'spills'.
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/// These slots are only used by the unwinder and calls to llvm.eh.return().
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/// Registers are ordered according to their frame offset.
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/// As offsets are negative, the largest offsets will be first.
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static void GetEHSpillList(SmallVectorImpl<std::pair<int,unsigned> > &SpillList,
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static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
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MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
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const TargetLowering *TL) {
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assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
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const int* EHSlot = XFI->getEHSpillSlot();
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SpillList.push_back(
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std::pair<int,unsigned>(MFI->getObjectOffset(EHSlot[0]),
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TL->getExceptionPointerRegister()));
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SpillList.push_back(
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std::pair<int,unsigned>(MFI->getObjectOffset(EHSlot[1]),
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TL->getExceptionSelectorRegister()));
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std::sort(SpillList.begin(), SpillList.end());
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SpillList.push_back(StackSlotInfo(EHSlot[0],
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MFI->getObjectOffset(EHSlot[0]),
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TL->getExceptionPointerRegister()));
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SpillList.push_back(StackSlotInfo(EHSlot[0],
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MFI->getObjectOffset(EHSlot[1]),
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TL->getExceptionSelectorRegister()));
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std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
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}
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static MachineMemOperand *
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getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) {
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
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flags, MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlignment(FrameIndex));
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return MMO;
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}
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/// Restore clobbered registers with their spill slot value.
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/// The SP will be adjusted at the same time, thus the SpillList must be ordered
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/// with the largest (negative) offsets first.
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static void
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RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj,
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SmallVectorImpl<std::pair<int,unsigned> > &SpillList) {
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SmallVectorImpl<StackSlotInfo> &SpillList) {
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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unsigned SpilledReg = SpillList[i].second;
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int SpillOffset = SpillList[i].first;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
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assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillList[i].Offset/4;
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IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
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int Offset = RemainingAdj - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpilledReg).addImm(Offset);
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
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.addImm(Offset)
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.addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
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MachineMemOperand::MOLoad));
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}
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}
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@ -203,6 +236,7 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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const AttributeSet &PAL = MF.getFunction()->getAttributes();
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if (PAL.hasAttrSomewhere(Attribute::Nest))
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
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// FIX: Needs addMemOperand() but can't use getFixedStack() or getStack().
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// Work out frame sizes.
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// We will adjust the SP in stages towards the final FrameSize.
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@ -234,26 +268,27 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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}
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// If necessary, save LR and FP to the stack, as we EXTSP.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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SmallVector<StackSlotInfo,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, saveLR, FP);
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// We want the nearest (negative) offsets first, so reverse list.
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std::reverse(SpillList.begin(),SpillList.end());
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std::reverse(SpillList.begin(), SpillList.end());
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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unsigned SpillReg = SpillList[i].second;
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int SpillOffset = SpillList[i].first;
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assert(SpillOffset % 4 == 0 && "Misaligned stack offset");
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assert(SpillOffset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillOffset/4;
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assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
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assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillList[i].Offset/4;
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IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
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emitFrameMoves);
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int Offset = Adjusted - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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MBB.addLiveIn(SpillReg);
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addReg(SpillReg, RegState::Kill)
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.addImm(Offset);
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MBB.addLiveIn(SpillList[i].Reg);
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BuildMI(MBB, MBBI, dl, TII.get(Opcode))
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.addReg(SpillList[i].Reg, RegState::Kill)
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.addImm(Offset)
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.addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
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MachineMemOperand::MOStore));
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if (emitFrameMoves) {
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unsigned DRegNum = MRI->getDwarfRegNum(SpillReg, true);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillOffset, NULL);
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unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
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EmitCfiOffset(MBB,MBBI,dl,TII,MMI, DRegNum, SpillList[i].Offset, NULL);
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}
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}
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@ -284,15 +319,15 @@ void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (XFI->hasEHSpillSlot()) {
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// The unwinder requires stack slot & CFI offsets for the exception info.
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// We do not save/spill these registers.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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SmallVector<StackSlotInfo,2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
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assert(SpillList.size()==2 && "Unexpected SpillList size");
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
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MRI->getDwarfRegNum(SpillList[0].second,true),
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SpillList[0].first, NULL);
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MRI->getDwarfRegNum(SpillList[0].Reg, true),
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SpillList[0].Offset, NULL);
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EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
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MRI->getDwarfRegNum(SpillList[1].second,true),
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SpillList[1].first, NULL);
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MRI->getDwarfRegNum(SpillList[1].Reg, true),
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SpillList[1].Offset, NULL);
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}
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}
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}
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@ -315,7 +350,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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if (RetOpcode == XCore::EH_RETURN) {
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// 'Restore' the exception info the unwinder has placed into the stack slots.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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SmallVector<StackSlotInfo,2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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@ -339,7 +374,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
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// If necessary, restore LR and FP from the stack, as we EXTSP.
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SmallVector<std::pair<int,unsigned>,2> SpillList;
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SmallVector<StackSlotInfo,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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@ -18,6 +18,7 @@
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCContext.h"
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@ -374,10 +375,18 @@ void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
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MachineMemOperand::MOStore,
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MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlignment(FrameIndex));
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BuildMI(MBB, I, DL, get(XCore::STWFI))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIndex)
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.addImm(0);
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.addImm(0)
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.addMemOperand(MMO);
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}
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void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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@ -388,9 +397,17 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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{
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
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MachineMemOperand::MOLoad,
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MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlignment(FrameIndex));
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BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
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.addFrameIndex(FrameIndex)
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.addImm(0);
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.addImm(0)
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.addMemOperand(MMO);
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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@ -67,13 +67,15 @@ static void InsertFPImmInst(MachineBasicBlock::iterator II,
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
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.addReg(FrameReg)
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.addImm(Offset);
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(FrameReg)
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.addImm(Offset);
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
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@ -93,7 +95,6 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II,
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
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RS->setUsed(ScratchOffset);
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TII.loadImmediate(MBB, II, ScratchOffset, Offset);
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@ -102,13 +103,15 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II,
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
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.addReg(FrameReg)
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.addReg(ScratchOffset, RegState::Kill);
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(FrameReg)
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.addReg(ScratchOffset, RegState::Kill);
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
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@ -127,18 +130,21 @@ static void InsertSPImmInst(MachineBasicBlock::iterator II,
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc dl = MI.getDebugLoc();
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bool isU6 = isImmU6(Offset);
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switch (MI.getOpcode()) {
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int NewOpcode;
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case XCore::LDWFI:
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NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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.addImm(Offset);
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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BuildMI(MBB, II, dl, TII.get(NewOpcode))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addImm(Offset);
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.addImm(Offset)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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@ -174,13 +180,15 @@ static void InsertSPConstInst(MachineBasicBlock::iterator II,
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case XCore::LDWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
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.addReg(ScratchBase, RegState::Kill)
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.addReg(ScratchOffset, RegState::Kill);
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::STWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
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.addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
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.addReg(ScratchBase, RegState::Kill)
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.addReg(ScratchOffset, RegState::Kill);
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.addReg(ScratchOffset, RegState::Kill)
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.addMemOperand(*MI.memoperands_begin());
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break;
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case XCore::LDAWFI:
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BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
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