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https://github.com/c64scene-ar/llvm-6502.git
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Redo LegalizeTypes soft float support for
SINT_TO_FP and UINT_TO_FP. This now produces the same code as LegalizeDAG (the previous code was based on a mistaken idea of what LegalizeDAG did in this case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53288 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
parent
452911c468
commit
b5508e4237
@ -20,9 +20,6 @@
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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using namespace llvm;
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/// GetFPLibCall - Return the right libcall for the given floating point type.
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@ -68,8 +65,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
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case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
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case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
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case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break;
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case ISD::SINT_TO_FP: R = SoftenFloatRes_SINT_TO_FP(N); break;
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case ISD::UINT_TO_FP: R = SoftenFloatRes_UINT_TO_FP(N); break;
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case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
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case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break;
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@ -268,104 +265,104 @@ SDOperand DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(SDNode *N) {
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N->getOperand(1), LHS, RHS, N->getOperand(4));
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}
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SDOperand DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
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bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
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MVT DestVT = N->getValueType(0);
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SDOperand DAGTypeLegalizer::SoftenFloatRes_SINT_TO_FP(SDNode *N) {
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SDOperand Op = N->getOperand(0);
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MVT RVT = N->getValueType(0);
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if (Op.getValueType() == MVT::i32) {
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// simple 32-bit [signed|unsigned] integer to float/double expansion
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// Get the stack frame index of a 8 byte buffer.
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SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
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// word offset constant for Hi/Lo address computation
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SDOperand Offset =
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DAG.getConstant(MVT(MVT::i32).getSizeInBits() / 8,
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TLI.getPointerTy());
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// set up Hi and Lo (into buffer) address based on endian
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SDOperand Hi = StackSlot;
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SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, Offset);
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if (TLI.isLittleEndian())
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std::swap(Hi, Lo);
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// if signed map to unsigned space
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SDOperand OpMapped;
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if (isSigned) {
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// constant used to invert sign bit (signed to unsigned mapping)
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SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
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OpMapped = DAG.getNode(ISD::XOR, MVT::i32, Op, SignBit);
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} else {
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OpMapped = Op;
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}
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// store the lo of the constructed double - based on integer input
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SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
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OpMapped, Lo, NULL, 0);
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// initial hi portion of constructed double
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SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
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// store the hi of the constructed double - biased exponent
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SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
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// load the constructed double
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SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
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// FP constant to bias correct the final result
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SDOperand Bias = DAG.getConstantFP(isSigned ?
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BitsToDouble(0x4330000080000000ULL)
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: BitsToDouble(0x4330000000000000ULL),
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MVT::f64);
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// subtract the bias
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SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
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// final result
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SDOperand Result;
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// handle final rounding
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if (DestVT == MVT::f64) {
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// do nothing
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Result = Sub;
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} else if (DestVT.bitsLT(MVT::f64)) {
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Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
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DAG.getIntPtrConstant(0));
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} else if (DestVT.bitsGT(MVT::f64)) {
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Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
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}
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return BitConvertToInteger(Result);
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}
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assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
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SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op);
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SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op), Op,
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DAG.getConstant(0, Op.getValueType()),
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ISD::SETLT);
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SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
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SignSet, Four, Zero);
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// If the sign bit of the integer is set, the large number will be treated
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// as a negative number. To counteract this, the dynamic code adds an
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// offset depending on the data type.
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uint64_t FF;
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch (Op.getValueType().getSimpleVT()) {
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default: assert(0 && "Unsupported integer type!");
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case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
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case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
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case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
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case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
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case MVT::i32:
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switch (RVT.getSimpleVT()) {
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case MVT::f32:
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LC = RTLIB::SINTTOFP_I32_F32;
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break;
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case MVT::f64:
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LC = RTLIB::SINTTOFP_I32_F64;
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break;
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default:
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break;
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}
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break;
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case MVT::i64:
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switch (RVT.getSimpleVT()) {
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case MVT::f32:
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LC = RTLIB::SINTTOFP_I64_F32;
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break;
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case MVT::f64:
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LC = RTLIB::SINTTOFP_I64_F64;
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break;
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case MVT::f80:
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LC = RTLIB::SINTTOFP_I64_F80;
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break;
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case MVT::ppcf128:
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LC = RTLIB::SINTTOFP_I64_PPCF128;
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break;
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default:
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break;
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}
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break;
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case MVT::i128:
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switch (RVT.getSimpleVT()) {
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case MVT::f32:
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LC = RTLIB::SINTTOFP_I128_F32;
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break;
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case MVT::f64:
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LC = RTLIB::SINTTOFP_I128_F64;
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break;
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case MVT::f80:
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LC = RTLIB::SINTTOFP_I128_F80;
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break;
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case MVT::ppcf128:
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LC = RTLIB::SINTTOFP_I128_PPCF128;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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if (TLI.isLittleEndian()) FF <<= 32;
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static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SINT_TO_FP!");
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SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
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CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
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SDOperand FudgeInReg;
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if (DestVT == MVT::f32)
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FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
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PseudoSourceValue::getConstantPool(), 0);
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else {
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FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestVT,
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DAG.getEntryNode(), CPIdx,
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PseudoSourceValue::getConstantPool(), 0,
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MVT::f32);
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return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false);
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}
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SDOperand DAGTypeLegalizer::SoftenFloatRes_UINT_TO_FP(SDNode *N) {
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SDOperand Op = N->getOperand(0);
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MVT RVT = N->getValueType(0);
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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switch (Op.getValueType().getSimpleVT()) {
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case MVT::i32:
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switch (RVT.getSimpleVT()) {
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case MVT::f32:
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LC = RTLIB::UINTTOFP_I32_F32;
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break;
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case MVT::f64:
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LC = RTLIB::UINTTOFP_I32_F64;
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break;
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default:
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break;
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}
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break;
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case MVT::i64:
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switch (RVT.getSimpleVT()) {
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case MVT::f32:
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LC = RTLIB::UINTTOFP_I64_F32;
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break;
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case MVT::f64:
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LC = RTLIB::UINTTOFP_I64_F64;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UINT_TO_FP!");
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return BitConvertToInteger(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
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return MakeLibCall(LC, TLI.getTypeToTransformTo(RVT), &Op, 1, false);
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}
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@ -539,6 +536,9 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
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case MVT::f64:
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LC = RTLIB::FPTOSINT_F64_I32;
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break;
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case MVT::ppcf128:
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LC = RTLIB::FPTOSINT_PPCF128_I32;
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break;
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default:
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break;
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}
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@ -602,6 +602,12 @@ SDOperand DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
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case MVT::f64:
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LC = RTLIB::FPTOUINT_F64_I32;
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break;
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case MVT::f80:
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LC = RTLIB::FPTOUINT_F80_I32;
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break;
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case MVT::ppcf128:
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LC = RTLIB::FPTOUINT_PPCF128_I32;
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break;
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default:
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break;
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}
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@ -341,7 +341,8 @@ private:
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SDOperand SoftenFloatRes_LOAD(SDNode *N);
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SDOperand SoftenFloatRes_SELECT(SDNode *N);
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SDOperand SoftenFloatRes_SELECT_CC(SDNode *N);
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SDOperand SoftenFloatRes_XINT_TO_FP(SDNode *N);
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SDOperand SoftenFloatRes_SINT_TO_FP(SDNode *N);
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SDOperand SoftenFloatRes_UINT_TO_FP(SDNode *N);
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// Operand Float to Integer Conversion.
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bool SoftenFloatOperand(SDNode *N, unsigned OpNo);
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