6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-08 19:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Qualify several calls to functions in the MVT namespace, for consistency.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37230 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2007-05-18 17:52:13 +00:00
parent 6092ca1556
commit b55757ec5f
4 changed files with 25 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@@ -2722,7 +2722,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case TargetLowering::Promote: { case TargetLowering::Promote: {
MVT::ValueType OVT = Tmp1.getValueType(); MVT::ValueType OVT = Tmp1.getValueType();
MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
@@ -2760,16 +2760,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::CTTZ: case ISD::CTTZ:
//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
DAG.getConstant(getSizeInBits(NVT), NVT), DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ); ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
break; break;
case ISD::CTLZ: case ISD::CTLZ:
// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1, Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
DAG.getConstant(getSizeInBits(NVT) - DAG.getConstant(MVT::getSizeInBits(NVT) -
getSizeInBits(OVT), NVT)); MVT::getSizeInBits(OVT), NVT));
break; break;
} }
break; break;
@@ -3527,7 +3527,8 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), DAG.getConstant(MVT::getSizeInBits(NVT) -
MVT::getSizeInBits(VT),
TLI.getShiftAmountTy())); TLI.getShiftAmountTy()));
break; break;
case ISD::CTPOP: case ISD::CTPOP:
@@ -3544,15 +3545,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
case ISD::CTTZ: case ISD::CTTZ:
// if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
ISD::SETEQ);
Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
break; break;
case ISD::CTLZ: case ISD::CTLZ:
//Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
Result = DAG.getNode(ISD::SUB, NVT, Tmp1, Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
DAG.getConstant(getSizeInBits(NVT) - DAG.getConstant(MVT::getSizeInBits(NVT) -
getSizeInBits(VT), NVT)); MVT::getSizeInBits(VT), NVT));
break; break;
} }
break; break;
@@ -4639,7 +4641,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
}; };
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
MVT::ValueType ShVT = TLI.getShiftAmountTy(); MVT::ValueType ShVT = TLI.getShiftAmountTy();
unsigned len = getSizeInBits(VT); unsigned len = MVT::getSizeInBits(VT);
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
SDOperand Tmp2 = DAG.getConstant(mask[i], VT); SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
@@ -4662,7 +4664,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
MVT::ValueType VT = Op.getValueType(); MVT::ValueType VT = Op.getValueType();
MVT::ValueType ShVT = TLI.getShiftAmountTy(); MVT::ValueType ShVT = TLI.getShiftAmountTy();
unsigned len = getSizeInBits(VT); unsigned len = MVT::getSizeInBits(VT);
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
@@ -4684,7 +4686,7 @@ SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
if (!TLI.isOperationLegal(ISD::CTPOP, VT) && if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
TLI.isOperationLegal(ISD::CTLZ, VT)) TLI.isOperationLegal(ISD::CTLZ, VT))
return DAG.getNode(ISD::SUB, VT, return DAG.getNode(ISD::SUB, VT,
DAG.getConstant(getSizeInBits(VT), VT), DAG.getConstant(MVT::getSizeInBits(VT), VT),
DAG.getNode(ISD::CTLZ, VT, Tmp3)); DAG.getNode(ISD::CTLZ, VT, Tmp3));
return DAG.getNode(ISD::CTPOP, VT, Tmp3); return DAG.getNode(ISD::CTPOP, VT, Tmp3);
} }

14
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@@ -310,14 +310,14 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
const VectorType *PTy = cast<VectorType>(V->getType()); const VectorType *PTy = cast<VectorType>(V->getType());
unsigned NumElts = PTy->getNumElements(); unsigned NumElts = PTy->getNumElements();
MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType()); MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
MVT::ValueType VecTy = getVectorType(EltTy, NumElts); MVT::ValueType VecTy = MVT::getVectorType(EltTy, NumElts);
// Divide the input until we get to a supported size. This will always // Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors. // end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) { while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
NumElts >>= 1; NumElts >>= 1;
NumVectorRegs <<= 1; NumVectorRegs <<= 1;
VecTy = getVectorType(EltTy, NumElts); VecTy = MVT::getVectorType(EltTy, NumElts);
} }
// Check that VecTy isn't a 1-element vector. // Check that VecTy isn't a 1-element vector.
@@ -1689,7 +1689,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
CaseRecVector& WorkList, CaseRecVector& WorkList,
Value* SV, Value* SV,
MachineBasicBlock* Default){ MachineBasicBlock* Default){
unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy()); unsigned IntPtrBits = MVT::getSizeInBits(TLI.getPointerTy());
Case& FrontCase = *CR.Range.first; Case& FrontCase = *CR.Range.first;
Case& BackCase = *(CR.Range.second-1); Case& BackCase = *(CR.Range.second-1);
@@ -4187,7 +4187,7 @@ static SDOperand getMemsetStringVal(MVT::ValueType VT,
SelectionDAG &DAG, TargetLowering &TLI, SelectionDAG &DAG, TargetLowering &TLI,
std::string &Str, unsigned Offset) { std::string &Str, unsigned Offset) {
uint64_t Val = 0; uint64_t Val = 0;
unsigned MSB = getSizeInBits(VT) / 8; unsigned MSB = MVT::getSizeInBits(VT) / 8;
if (TLI.isLittleEndian()) if (TLI.isLittleEndian())
Offset = Offset + MSB - 1; Offset = Offset + MSB - 1;
for (unsigned i = 0; i != MSB; ++i) { for (unsigned i = 0; i != MSB; ++i) {
@@ -4241,7 +4241,7 @@ static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
unsigned NumMemOps = 0; unsigned NumMemOps = 0;
while (Size != 0) { while (Size != 0) {
unsigned VTSize = getSizeInBits(VT) / 8; unsigned VTSize = MVT::getSizeInBits(VT) / 8;
while (VTSize > Size) { while (VTSize > Size) {
VT = (MVT::ValueType)((unsigned)VT - 1); VT = (MVT::ValueType)((unsigned)VT - 1);
VTSize >>= 1; VTSize >>= 1;
@@ -4280,7 +4280,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
unsigned Offset = 0; unsigned Offset = 0;
for (unsigned i = 0; i < NumMemOps; i++) { for (unsigned i = 0; i < NumMemOps; i++) {
MVT::ValueType VT = MemOps[i]; MVT::ValueType VT = MemOps[i];
unsigned VTSize = getSizeInBits(VT) / 8; unsigned VTSize = MVT::getSizeInBits(VT) / 8;
SDOperand Value = getMemsetValue(Op2, VT, DAG); SDOperand Value = getMemsetValue(Op2, VT, DAG);
SDOperand Store = DAG.getStore(getRoot(), Value, SDOperand Store = DAG.getStore(getRoot(), Value,
getMemBasePlusOffset(Op1, Offset, DAG, TLI), getMemBasePlusOffset(Op1, Offset, DAG, TLI),
@@ -4321,7 +4321,7 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
for (unsigned i = 0; i < NumMemOps; i++) { for (unsigned i = 0; i < NumMemOps; i++) {
MVT::ValueType VT = MemOps[i]; MVT::ValueType VT = MemOps[i];
unsigned VTSize = getSizeInBits(VT) / 8; unsigned VTSize = MVT::getSizeInBits(VT) / 8;
SDOperand Value, Chain, Store; SDOperand Value, Chain, Store;
if (CopyFromStr) { if (CopyFromStr) {

2
lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@@ -145,7 +145,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
else else
Op += "<null:" + itostr(M->getOffset()) + ">"; Op += "<null:" + itostr(M->getOffset()) + ">";
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) { } else if (const VTSDNode *N = dyn_cast<VTSDNode>(Node)) {
Op = Op + " VT=" + getValueTypeString(N->getVT()); Op = Op + " VT=" + MVT::getValueTypeString(N->getVT());
} else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) { } else if (const StringSDNode *N = dyn_cast<StringSDNode>(Node)) {
Op = Op + "\"" + N->getValue() + "\""; Op = Op + "\"" + N->getValue() + "\"";
} else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) { } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node)) {

4
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@@ -299,12 +299,12 @@ unsigned TargetLowering::getVectorTypeBreakdown(const VectorType *PTy,
// Divide the input until we get to a supported size. This will always // Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors. // end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && !isTypeLegal(getVectorType(EltTy, NumElts))) { while (NumElts > 1 && !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
NumElts >>= 1; NumElts >>= 1;
NumVectorRegs <<= 1; NumVectorRegs <<= 1;
} }
MVT::ValueType VT = getVectorType(EltTy, NumElts); MVT::ValueType VT = MVT::getVectorType(EltTy, NumElts);
if (!isTypeLegal(VT)) if (!isTypeLegal(VT))
VT = EltTy; VT = EltTy;
PTyElementVT = VT; PTyElementVT = VT;