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Add xor reg-reg pattern

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75915 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2009-07-16 13:31:28 +00:00
parent 26ba0b1ec5
commit b573f99ab7
3 changed files with 19 additions and 0 deletions
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7
lib/Target/SystemZ/SystemZInstrInfo.td
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@ -77,5 +77,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
} }
// FIXME: provide patterns for masked or-with-imm // FIXME: provide patterns for masked or-with-imm
let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
// FIXME: Provide proper encoding!
def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"xgr\t{$dst, $src2}",
[(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
}
} // Defs = [PSW] } // Defs = [PSW]
} // isTwoAddress = 1 } // isTwoAddress = 1

6
test/CodeGen/SystemZ/02-RetXor.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = xor i64 %a, %b
ret i64 %c
}

6
test/CodeGen/SystemZ/02-RetXorImm.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = xor i64 %a, 1
ret i64 %c
}