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Do not lose mem_operands while lowering VLD / VST intrinsics.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-04-19 00:04:03 +00:00
parent 05a5ff1f00
commit b58a340fa2
4 changed files with 44 additions and 9 deletions
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2
test/CodeGen/ARM/vld1.ll
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@ -133,8 +133,6 @@ declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
; Do not crash if the vld1 result is not used.
define void @unused_vld1_result() {
entry:
;CHECK: unused_vld1_result
;CHECK: vld1.32
%0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1)
call void @llvm.trap()
unreachable

10
test/CodeGen/ARM/vldlane.ll
View File

@ -491,7 +491,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo
; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
;CHECK: test_qqqq_regsequence_subreg
;CHECK: vld3.16
%tmp63 = extractvalue [6 x i64] %b, 5
@ -500,8 +500,12 @@ define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
%ins67 = or i128 %tmp65, 0
%tmp78 = bitcast i128 %ins67 to <8 x i16>
%vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2)
call void @llvm.trap()
unreachable
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0
%tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1
%tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2
%tmp6 = add <8 x i16> %tmp3, %tmp4
%tmp7 = add <8 x i16> %tmp5, %tmp6
ret <8 x i16> %tmp7
}
declare void @llvm.trap() nounwind