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ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-16 19:12:24 +00:00
parent 48b368bcd5
commit b598b04409
1 changed files with 12 additions and 0 deletions
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12
lib/Target/ARM/ARMInstrInfo.td
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@ -5038,6 +5038,18 @@ def : ARMInstAlias<"lsl${s}${p} $Rm, $imm",
(LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"ror${s}${p} $Rm, $imm",
(RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>;
def : ARMInstAlias<"asr${s}${p} $Rn, $Rm",
(ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm",
(LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm",
(LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
(RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
cc_out:$s)>;
// 'mul' instruction can be specified with only two operands.