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ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lauro Ramos Venancio
2007-01-31 13:12:46 +00:00
parent 193f850880
commit b5b84f92bf
4 changed files with 12 additions and 13 deletions
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17
lib/Target/ARM/ARMRegisterInfo.cpp
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@ -573,7 +573,6 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
// There is alloca()'s in this function, must reference off the frame // There is alloca()'s in this function, must reference off the frame
// pointer instead. // pointer instead.
FrameReg = getFrameRegister(MF); FrameReg = getFrameRegister(MF);
if (STI.isTargetDarwin())
Offset -= AFI->getFramePtrSpillOffset(); Offset -= AFI->getFramePtrSpillOffset();
} }
@ -882,6 +881,12 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
} }
} }
if (hasFP(MF)) {
MF.changePhyRegUsed(FramePtr, true);
NumGPRSpills++;
CanEliminateFrame = false;
}
if (!CanEliminateFrame) { if (!CanEliminateFrame) {
AFI->setHasStackFrame(true); AFI->setHasStackFrame(true);
@ -895,11 +900,6 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF) const {
ForceLRSpill = false; ForceLRSpill = false;
} }
if (STI.isTargetDarwin()) {
MF.changePhyRegUsed(FramePtr, true);
NumGPRSpills++;
}
// If stack and double are 8-byte aligned and we are spilling an odd number // If stack and double are 8-byte aligned and we are spilling an odd number
// of GPRs. Spill one extra callee save GPR so we won't have to pad between // of GPRs. Spill one extra callee save GPR so we won't have to pad between
// the integer and double callee save areas. // the integer and double callee save areas.
@ -1030,7 +1030,7 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
++MBBI; ++MBBI;
// Point FP to the stack slot that contains the previous FP. // Point FP to the stack slot that contains the previous FP.
if (STI.isTargetDarwin()) if (hasFP(MF))
BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr) BuildMI(MBB, MBBI, TII.get(isThumb ? ARM::tADDrSPi : ARM::ADDri), FramePtr)
.addFrameIndex(FramePtrSpillFI).addImm(0); .addFrameIndex(FramePtrSpillFI).addImm(0);
@ -1116,7 +1116,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
if (isThumb) if (isThumb)
emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII); emitSPUpdate(MBB, MBBI, NumBytes, isThumb, TII);
else { else {
if (STI.isTargetDarwin()) { if (hasFP(MF)){
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
// Reset SP based on frame pointer only if the stack frame extends beyond // Reset SP based on frame pointer only if the stack frame extends beyond
// frame pointer stack slot. // frame pointer stack slot.
@ -1131,7 +1131,6 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
} else if (NumBytes) { } else if (NumBytes) {
emitSPUpdate(MBB, MBBI, NumBytes, false, TII); emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
} }
// Move SP to start of integer callee save spill area 2. // Move SP to start of integer callee save spill area 2.
movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI); movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII); emitSPUpdate(MBB, MBBI, AFI->getDPRCalleeSavedAreaSize(), false, TII);

2
test/CodeGen/ARM/hello.ll
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@ -1,6 +1,6 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-linux | grep mov | wc -l | grep 1 && ; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-linux | grep mov | wc -l | grep 1 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin | grep mov | wc -l | grep 2 ; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin --disable-fp-elim | grep mov | wc -l | grep 2
%str = internal constant [12 x sbyte] c"Hello World\00" %str = internal constant [12 x sbyte] c"Hello World\00"

2
test/CodeGen/ARM/insn-sched1.ll
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@ -1,5 +1,5 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm -mattr=+v6 && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm -mattr=+v6 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin -mattr=+v6 | grep mov | wc -l | grep 2 ; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin -mattr=+v6 --disable-fp-elim | grep mov | wc -l | grep 2
int %test(int %x) { int %test(int %x) {
%tmp = cast int %x to short %tmp = cast int %x to short

2
test/CodeGen/ARM/ldm.ll
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@ -1,7 +1,7 @@
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm &&
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldmia" | wc -l | grep 2 && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldmia" | wc -l | grep 2 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldmib" | wc -l | grep 1 && ; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep "ldmib" | wc -l | grep 1 &&
; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin | grep "ldmfd sp\!" | wc -l | grep 3 ; RUN: llvm-upgrade < %s | llvm-as | llc -mtriple=arm-apple-darwin --disable-fp-elim | grep "ldmfd sp\!" | wc -l | grep 3
%X = external global [0 x int] %X = external global [0 x int]