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Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
for needing the DAG node to print pre-legalize extended value types, and to get better debug messages with target-specific nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37656 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -113,7 +113,7 @@ namespace {
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bool AddTo = true) {
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bool AddTo = true) {
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assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
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assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
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++NodesCombined;
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++NodesCombined;
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DOUT << "\nReplacing.1 "; DEBUG(N->dump());
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DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
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DOUT << " and " << NumTo-1 << " other values\n";
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DOUT << " and " << NumTo-1 << " other values\n";
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std::vector<SDNode*> NowDead;
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std::vector<SDNode*> NowDead;
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@ -164,7 +164,7 @@ namespace {
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// Replace the old value with the new one.
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// Replace the old value with the new one.
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++NodesCombined;
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++NodesCombined;
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DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
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DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
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DOUT << '\n';
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DOUT << '\n';
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@ -592,7 +592,7 @@ void DAGCombiner::Run(bool RunningAfterLegalize) {
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RV.Val->getOpcode() != ISD::DELETED_NODE &&
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RV.Val->getOpcode() != ISD::DELETED_NODE &&
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"Node was deleted but visit returned new node!");
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"Node was deleted but visit returned new node!");
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DOUT << "\nReplacing.3 "; DEBUG(N->dump());
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DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
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DOUT << '\n';
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DOUT << '\n';
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std::vector<SDNode*> NowDead;
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std::vector<SDNode*> NowDead;
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@ -3314,7 +3314,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
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Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
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Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
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++PreIndexedNodes;
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++PreIndexedNodes;
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++NodesCombined;
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++NodesCombined;
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DOUT << "\nReplacing.4 "; DEBUG(N->dump());
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DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
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DOUT << '\n';
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DOUT << '\n';
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std::vector<SDNode*> NowDead;
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std::vector<SDNode*> NowDead;
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@ -3445,7 +3445,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
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: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
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: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
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++PostIndexedNodes;
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++PostIndexedNodes;
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++NodesCombined;
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++NodesCombined;
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DOUT << "\nReplacing.5 "; DEBUG(N->dump());
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DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
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DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
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DOUT << '\n';
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DOUT << '\n';
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std::vector<SDNode*> NowDead;
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std::vector<SDNode*> NowDead;
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@ -476,7 +476,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
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switch (Node->getOpcode()) {
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switch (Node->getOpcode()) {
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default:
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default:
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#ifndef NDEBUG
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#ifndef NDEBUG
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Node->dump();
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Node->dump(&DAG);
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#endif
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#endif
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assert(0 && "This target-independent node should have been selected!");
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: // fall thru
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case ISD::EntryToken: // fall thru
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@ -512,7 +512,7 @@ void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
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// not subject to CSE.
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// not subject to CSE.
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if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
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if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
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!N->isTargetOpcode()) {
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!N->isTargetOpcode()) {
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N->dump();
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N->dump(this);
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cerr << "\n";
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cerr << "\n";
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assert(0 && "Node is not in map!");
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assert(0 && "Node is not in map!");
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}
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}
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@ -356,7 +356,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
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bool rev = false;
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bool rev = false;
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bool inv = false;
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bool inv = false;
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switch(CC) {
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switch(CC) {
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default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
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default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
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case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
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case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
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Opc = Alpha::CMPTEQ; break;
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Opc = Alpha::CMPTEQ; break;
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case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
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case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
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@ -470,7 +470,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
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switch (TypeBeingLoaded) {
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switch (TypeBeingLoaded) {
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default:
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default:
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#ifndef NDEBUG
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#ifndef NDEBUG
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N->dump();
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N->dump(CurDAG);
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#endif
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#endif
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assert(0 && "Cannot load this type!");
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assert(0 && "Cannot load this type!");
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case MVT::i1: { // this is a bool
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case MVT::i1: { // this is a bool
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