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R600/SI: Refactor fneg / fabs patterns

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215746 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-08-15 18:42:11 +00:00
parent 2726e7d60b
commit b5cb5e29a7
1 changed files with 17 additions and 22 deletions
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39
lib/Target/R600/SIInstructions.td
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@ -2334,33 +2334,28 @@ def : Pat <
(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
>; >;
def FABS_SI : AMDGPUShaderInst < class SIUnaryCustomInsertInst<string name, SDPatternOperator node,
(outs VReg_32:$dst), ValueType vt,
(ins VSrc_32:$src0), RegisterClass dstrc,
"FABS_SI $dst, $src0", RegisterClass srcrc> :
[] AMDGPUShaderInst<
> { (outs dstrc:$dst),
(ins srcrc:$src0),
name#" $dst, $src0",
[(set vt:$dst, (node vt:$src0))]> {
let usesCustomInserter = 1; let usesCustomInserter = 1;
} }
def : Pat < def FABS_SI : SIUnaryCustomInsertInst<"FABS_SI", fabs,
(fabs f32:$src), f32, VReg_32, VSrc_32>;
(FABS_SI f32:$src) def FNEG_SI : SIUnaryCustomInsertInst<"FNEG_SI", fneg,
>; f32, VReg_32, VSrc_32>;
def FNEG_SI : AMDGPUShaderInst < def FABS64_SI : SIUnaryCustomInsertInst<"FABS64_SI", fabs,
(outs VReg_32:$dst), f64, VReg_64, VSrc_64>;
(ins VSrc_32:$src0), def FNEG64_SI : SIUnaryCustomInsertInst<"FNEG64_SI", fneg,
"FNEG_SI $dst, $src0", f64, VReg_64, VSrc_64>;
[]
> {
let usesCustomInserter = 1;
}
def : Pat <
(fneg f32:$src),
(FNEG_SI f32:$src)
>;
/********** ================== **********/ /********** ================== **********/
/********** Immediate Patterns **********/ /********** Immediate Patterns **********/