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Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53502 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-07-12 01:38:51 +00:00
parent cddc11e757
commit b5eec33dcd
7 changed files with 34 additions and 77 deletions
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5
include/llvm/CodeGen/SelectionDAGISel.h
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@ -30,7 +30,6 @@ namespace llvm {
class FunctionLoweringInfo;
class HazardRecognizer;
class CollectorMetadata;
class ScheduleDAG;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
@ -192,9 +191,9 @@ private:
void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
/// Pick a safe ordering for instructions for each target node in the
/// Pick a safe ordering and emit instructions for each target node in the
/// graph.
ScheduleDAG *Schedule(SelectionDAG &DAG);
void ScheduleAndEmitDAG(SelectionDAG &DAG);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.

2
include/llvm/Support/Timer.h
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@ -132,8 +132,6 @@ public:
///
struct NamedRegionTimer : public TimeRegion {
explicit NamedRegionTimer(const std::string &Name);
explicit NamedRegionTimer(const std::string &Name,
const std::string &GroupName);
};

5
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -1135,11 +1135,6 @@ void ScheduleDAG::dumpSchedule() const {
///
MachineBasicBlock *ScheduleDAG::Run() {
Schedule();
DOUT << "*** Final schedule ***\n";
DEBUG(dumpSchedule());
DOUT << "\n";
return BB;
}

7
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
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@ -99,6 +99,13 @@ void ScheduleDAGList::Schedule() {
ListScheduleTopDown();
AvailableQueue->releaseState();
DOUT << "*** Final schedule ***\n";
DEBUG(dumpSchedule());
DOUT << "\n";
// Emit in scheduled order
EmitSchedule();
}
//===----------------------------------------------------------------------===//

7
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -204,6 +204,13 @@ void ScheduleDAGRRList::Schedule() {
if (!Fast)
CommuteNodesToReducePressure();
DOUT << "*** Final schedule ***\n";
DEBUG(dumpSchedule());
DOUT << "\n";
// Emit in scheduled order
EmitSchedule();
}
/// CommuteNodesToReducePressure - If a node is two-address and commutable, and

49
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -5284,11 +5284,10 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Lowered selection DAG:\n";
DEBUG(DAG.dump());
std::string GroupName = "Instruction Selection and Scheduling";
// Run the DAG combiner in pre-legalize mode.
if (TimePassesIsEnabled) {
NamedRegionTimer T("DAG Combining 1", GroupName);
NamedRegionTimer T("DAG Combining 1");
DAG.Combine(false, *AA);
} else {
DAG.Combine(false, *AA);
@ -5305,7 +5304,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
}
if (TimePassesIsEnabled) {
NamedRegionTimer T("DAG Legalization", GroupName);
NamedRegionTimer T("DAG Legalization");
DAG.Legalize();
} else {
DAG.Legalize();
@ -5316,7 +5315,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Run the DAG combiner in post-legalize mode.
if (TimePassesIsEnabled) {
NamedRegionTimer T("DAG Combining 2", GroupName);
NamedRegionTimer T("DAG Combining 2");
DAG.Combine(true, *AA);
} else {
DAG.Combine(true, *AA);
@ -5333,41 +5332,24 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Third, instruction select all of the operations to machine code, adding the
// code to the MachineBasicBlock.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Selection", GroupName);
NamedRegionTimer T("Instruction Selection");
InstructionSelect(DAG);
} else {
InstructionSelect(DAG);
}
// Schedule machine code.
ScheduleDAG *Scheduler;
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Scheduling", GroupName);
Scheduler = Schedule(DAG);
} else {
Scheduler = Schedule(DAG);
}
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Creation", GroupName);
Scheduler->EmitSchedule();
NamedRegionTimer T("Instruction Scheduling");
ScheduleAndEmitDAG(DAG);
} else {
Scheduler->EmitSchedule();
}
// Free the scheduler state.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName);
delete Scheduler;
} else {
delete Scheduler;
ScheduleAndEmitDAG(DAG);
}
// Perform target specific isel post processing.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
NamedRegionTimer T("Instruction Selection Post Processing");
InstructionSelectPostProcessing(DAG);
} else {
InstructionSelectPostProcessing(DAG);
@ -5615,10 +5597,10 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
}
/// Schedule - Pick a safe ordering for instructions for each
//===----------------------------------------------------------------------===//
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
/// target node in the graph.
///
ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
@ -5628,11 +5610,12 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
RegisterScheduler::setDefault(Ctor);
}
ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
BB = Scheduler->Run();
ScheduleDAG *SL = Ctor(this, &DAG, BB, FastISel);
BB = SL->Run();
if (ViewSUnitDAGs) Scheduler->viewGraph();
return Scheduler;
if (ViewSUnitDAGs) SL->viewGraph();
delete SL;
}

36
lib/Support/Timer.cpp
View File

@ -182,51 +182,19 @@ void Timer::addPeakMemoryMeasurement() {
// NamedRegionTimer Implementation
//===----------------------------------------------------------------------===//
namespace {
typedef std::map<std::string, Timer> Name2Timer;
typedef std::map<std::string, std::pair<TimerGroup, Name2Timer> > Name2Pair;
}
static ManagedStatic<Name2Timer> NamedTimers;
static ManagedStatic<Name2Pair> NamedGroupedTimers;
static ManagedStatic<std::map<std::string, Timer> > NamedTimers;
static Timer &getNamedRegionTimer(const std::string &Name) {
Name2Timer::iterator I = NamedTimers->find(Name);
std::map<std::string, Timer>::iterator I = NamedTimers->find(Name);
if (I != NamedTimers->end())
return I->second;
return NamedTimers->insert(I, std::make_pair(Name, Timer(Name)))->second;
}
static Timer &getNamedRegionTimer(const std::string &Name,
const std::string &GroupName) {
Name2Pair::iterator I = NamedGroupedTimers->find(GroupName);
if (I == NamedGroupedTimers->end()) {
TimerGroup TG(GroupName);
std::pair<TimerGroup, Name2Timer> Pair(TG, Name2Timer());
I = NamedGroupedTimers->insert(I, std::make_pair(GroupName, Pair));
}
Name2Timer::iterator J = I->second.second.find(Name);
if (J == I->second.second.end())
J = I->second.second.insert(J,
std::make_pair(Name,
Timer(Name,
I->second.first)));
return J->second;
}
NamedRegionTimer::NamedRegionTimer(const std::string &Name)
: TimeRegion(getNamedRegionTimer(Name)) {}
NamedRegionTimer::NamedRegionTimer(const std::string &Name,
const std::string &GroupName)
: TimeRegion(getNamedRegionTimer(Name, GroupName)) {}
//===----------------------------------------------------------------------===//
// TimerGroup Implementation