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Assembly parsing for 4-register variant of VLD1.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-10-21 20:35:01 +00:00
parent 65f73abf07
commit b6310316db
8 changed files with 48 additions and 31 deletions
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4
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -142,8 +142,8 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 ,true},
{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 ,true},
{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 ,true},
{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 ,true},
{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 ,false},
{ ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 ,false},
{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 ,false},
{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 ,false},

17
lib/Target/ARM/ARMInstrNEON.td
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@ -93,6 +93,14 @@ def VecListThreeDAsmOperand : AsmOperandClass {
def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
let ParserMatchClass = VecListThreeDAsmOperand;
}
// Register list of four sequential D registers.
def VecListFourDAsmOperand : AsmOperandClass {
let Name = "VecListFourD";
let ParserMethod = "parseVectorList";
}
def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
let ParserMatchClass = VecListFourDAsmOperand;
}
//===----------------------------------------------------------------------===//
// NEON-specific DAG Nodes.
@ -357,18 +365,17 @@ def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
// ...with 4 registers
class VLD1D4<bits<4> op7_4, string Dt>
: NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
: NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
(ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
"\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
"$Vd, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";
}
class VLD1D4WB<bits<4> op7_4, string Dt>
: NLdSt<0,0b10,0b0010,op7_4,
(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
: NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
"\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
"$Vd, $Rn$Rm", "$Rn.addr = $wb",
[]> {
let Inst{5-4} = Rn{5-4};
let DecoderMethod = "DecodeVLDInstruction";

12
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -925,6 +925,11 @@ public:
return VectorList.Count == 3;
}
bool isVecListFourD() const {
if (Kind != k_VectorList) return false;
return VectorList.Count == 4;
}
bool isVectorIndex8() const {
if (Kind != k_VectorIndex) return false;
return VectorIndex.Val < 8;
@ -1531,6 +1536,13 @@ public:
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));

24
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1959,14 +1959,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Second output register
switch (Inst.getOpcode()) {
case ARM::VLD1d8Q:
case ARM::VLD1d16Q:
case ARM::VLD1d32Q:
case ARM::VLD1d64Q:
case ARM::VLD1d8Q_UPD:
case ARM::VLD1d16Q_UPD:
case ARM::VLD1d32Q_UPD:
case ARM::VLD1d64Q_UPD:
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
@ -2020,14 +2012,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Third output register
switch(Inst.getOpcode()) {
case ARM::VLD1d8Q:
case ARM::VLD1d16Q:
case ARM::VLD1d32Q:
case ARM::VLD1d64Q:
case ARM::VLD1d8Q_UPD:
case ARM::VLD1d16Q_UPD:
case ARM::VLD1d32Q_UPD:
case ARM::VLD1d64Q_UPD:
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
@ -2070,14 +2054,6 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
// Fourth output register
switch (Inst.getOpcode()) {
case ARM::VLD1d8Q:
case ARM::VLD1d16Q:
case ARM::VLD1d32Q:
case ARM::VLD1d64Q:
case ARM::VLD1d8Q_UPD:
case ARM::VLD1d16Q_UPD:
case ARM::VLD1d32Q_UPD:
case ARM::VLD1d64Q_UPD:
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:

11
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -1014,3 +1014,14 @@ void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
}
void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
<< getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
}

1
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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@ -132,6 +132,7 @@ public:
void printVectorListOne(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVectorListThree(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
};
} // end namespace llvm

9
test/MC/ARM/neon-vld-encoding.s
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@ -12,6 +12,10 @@
vld1.16 {d4, d5, d6}, [r3, :64]
vld1.32 {d5, d6, d7}, [r3]
vld1.64 {d6, d7, d8}, [r3, :64]
vld1.8 {d1, d2, d3, d4}, [r3]
vld1.16 {d4, d5, d6, d7}, [r3, :64]
vld1.32 {d5, d6, d7, d8}, [r3]
vld1.64 {d6, d7, d8, d9}, [r3, :64]
@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4]
@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4]
@ -25,6 +29,11 @@
@ CHECK: vld1.16 {d4, d5, d6}, [r3, :64] @ encoding: [0x5f,0x46,0x23,0xf4]
@ CHECK: vld1.32 {d5, d6, d7}, [r3] @ encoding: [0x8f,0x56,0x23,0xf4]
@ CHECK: vld1.64 {d6, d7, d8}, [r3, :64] @ encoding: [0xdf,0x66,0x23,0xf4]
@ CHECK: vld1.8 {d1, d2, d3, d4}, [r3] @ encoding: [0x0f,0x12,0x23,0xf4]
@ CHECK: vld1.16 {d4, d5, d6, d7}, [r3, :64] @ encoding: [0x5f,0x42,0x23,0xf4]
@ CHECK: vld1.32 {d5, d6, d7, d8}, [r3] @ encoding: [0x8f,0x52,0x23,0xf4]
@ CHECK: vld1.64 {d6, d7, d8, d9}, [r3, :64] @ encoding: [0xdf,0x62,0x23,0xf4]
@ vld2.8 {d16, d17}, [r0, :64]
@ vld2.16 {d16, d17}, [r0, :128]

1
utils/TableGen/EDEmitter.cpp
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@ -574,6 +574,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
REG("VecListOneD");
REG("VecListTwoD");
REG("VecListThreeD");
REG("VecListFourD");
IMM("i32imm");
IMM("i32imm_hilo16");