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[mips] Add instruction selection pattern for (seteq $LHS, 0).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181459 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-05-08 19:38:04 +00:00
parent 146f336272
commit b637b9f89e
2 changed files with 13 additions and 0 deletions
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2
lib/Target/Mips/MipsInstrInfo.td
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@ -1263,6 +1263,8 @@ defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
// setcc patterns
multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
Instruction SLTuOp, Register ZEROReg> {
def : MipsPat<(seteq RC:$lhs, 0),
(SLTiuOp RC:$lhs, 1)>;
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),

11
test/CodeGen/Mips/setcc-se.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc -march=mipsel < %s | FileCheck %s
; CHECK: seteq0:
; CHECK: sltiu ${{[0-9]+}}, $4, 1
define i32 @seteq0(i32 %a) {
entry:
%cmp = icmp eq i32 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
}