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Added temp flag -misched-bench for staging in default changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-09-26 05:53:35 +00:00
parent 7394a7c0c2
commit b6ac11cd03
5 changed files with 22 additions and 4 deletions
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3
include/llvm/Target/TargetSubtargetInfo.h
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@ -56,6 +56,9 @@ public:
return 0;
}
/// \brief Temporary API to test migration to MI scheduler.
bool useMachineScheduler() const;
/// \brief True if the subtarget should run MachineScheduler after aggressive
/// coalescing.
///

2
lib/CodeGen/Passes.cpp
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@ -236,7 +236,7 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
// Temporarily disable experimental passes.
const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
if (!ST.enableMachineScheduler())
if (!ST.useMachineScheduler())
disablePass(&MachineSchedulerID);
}

2
lib/CodeGen/RegisterCoalescer.cpp
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@ -2199,7 +2199,7 @@ bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
if (EnableGlobalCopies == cl::BOU_UNSET)
JoinGlobalCopies = ST.enableMachineScheduler();
JoinGlobalCopies = ST.useMachineScheduler();
else
JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -230,7 +230,7 @@ namespace llvm {
const TargetLowering *TLI = IS->getTargetLowering();
const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
TLI->getSchedulingPreference() == Sched::Source)
return createSourceListDAGScheduler(IS, OptLevel);
if (TLI->getSchedulingPreference() == Sched::RegPressure)

17
lib/Target/TargetSubtargetInfo.cpp
View File

@ -11,6 +11,7 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
@ -22,6 +23,21 @@ TargetSubtargetInfo::TargetSubtargetInfo() {}
TargetSubtargetInfo::~TargetSubtargetInfo() {}
// Temporary option to compare overall performance change when moving from the
// SD scheduler to the MachineScheduler pass pipeline. It should be removed
// before 3.4. The normal way to enable/disable the MachineScheduling pass
// itself is by using -enable-misched. For targets that already use MI sched
// (via MySubTarget::enableMachineScheduler()) -misched-bench=false negates the
// subtarget hook.
static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
bool TargetSubtargetInfo::useMachineScheduler() const {
if (BenchMachineSched.getNumOccurrences())
return BenchMachineSched;
return enableMachineScheduler();
}
bool TargetSubtargetInfo::enableMachineScheduler() const {
return false;
}
@ -38,4 +54,3 @@ bool TargetSubtargetInfo::enablePostRAScheduler(
bool TargetSubtargetInfo::useAA() const {
return false;
}