From b6cbecd27298ca795eba350ee68fb82c4f4e422a Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 23 Mar 2014 05:35:00 +0000 Subject: [PATCH] [PowerPC] Make use of VSX f64 <-> i64 conversion instructions When VSX is available, these instructions should be used in preference to the older variants that only have access to the scalar floating-point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204559 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCInstrVSX.td | 18 ++++++---- test/CodeGen/PowerPC/float-to-int.ll | 49 ++++++++++++++++++++++++++++ test/CodeGen/PowerPC/i32-to-float.ll | 25 ++++++++++++++ test/CodeGen/PowerPC/i64-to-float.ll | 25 ++++++++++++++ 4 files changed, 111 insertions(+), 6 deletions(-) diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td index cfc526ef805..63ea15db710 100644 --- a/lib/Target/PowerPC/PPCInstrVSX.td +++ b/lib/Target/PowerPC/PPCInstrVSX.td @@ -414,25 +414,31 @@ let Uses = [RM] in { "xscvdpsp $XT, $XB", IIC_VecFP, []>; def XSCVDPSXDS : XX2Form<60, 344, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvdpsxds $XT, $XB", IIC_VecFP, []>; + "xscvdpsxds $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfctidz f64:$XB))]>; def XSCVDPSXWS : XX2Form<60, 88, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvdpsxws $XT, $XB", IIC_VecFP, []>; + "xscvdpsxws $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfctiwz f64:$XB))]>; def XSCVDPUXDS : XX2Form<60, 328, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvdpuxds $XT, $XB", IIC_VecFP, []>; + "xscvdpuxds $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfctiduz f64:$XB))]>; def XSCVDPUXWS : XX2Form<60, 72, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvdpuxws $XT, $XB", IIC_VecFP, []>; + "xscvdpuxws $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfctiwuz f64:$XB))]>; def XSCVSPDP : XX2Form<60, 329, (outs vsrc:$XT), (ins vsrc:$XB), "xscvspdp $XT, $XB", IIC_VecFP, []>; def XSCVSXDDP : XX2Form<60, 376, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvsxddp $XT, $XB", IIC_VecFP, []>; + "xscvsxddp $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfcfid f64:$XB))]>; def XSCVUXDDP : XX2Form<60, 360, (outs vsrc:$XT), (ins vsrc:$XB), - "xscvuxddp $XT, $XB", IIC_VecFP, []>; + "xscvuxddp $XT, $XB", IIC_VecFP, + [(set f64:$XT, (PPCfcfidu f64:$XB))]>; def XVCVDPSP : XX2Form<60, 393, (outs vsrc:$XT), (ins vsrc:$XB), diff --git a/test/CodeGen/PowerPC/float-to-int.ll b/test/CodeGen/PowerPC/float-to-int.ll index 39cd4f929f8..9c897cb96e7 100644 --- a/test/CodeGen/PowerPC/float-to-int.ll +++ b/test/CodeGen/PowerPC/float-to-int.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -12,6 +13,12 @@ define i64 @foo(float %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo +; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo2(double %a) nounwind { @@ -23,6 +30,12 @@ define i64 @foo2(double %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo2 +; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo3(float %a) nounwind { @@ -34,6 +47,12 @@ define i64 @foo3(float %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo3 +; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo4(double %a) nounwind { @@ -45,6 +64,12 @@ define i64 @foo4(double %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo4 +; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i32 @goo(float %a) nounwind { @@ -56,6 +81,12 @@ define i32 @goo(float %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo +; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo2(double %a) nounwind { @@ -67,6 +98,12 @@ define i32 @goo2(double %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo2 +; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo3(float %a) nounwind { @@ -78,6 +115,12 @@ define i32 @goo3(float %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo3 +; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo4(double %a) nounwind { @@ -89,5 +132,11 @@ define i32 @goo4(double %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo4 +; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } diff --git a/test/CodeGen/PowerPC/i32-to-float.ll b/test/CodeGen/PowerPC/i32-to-float.ll index 2707d0352de..371f4e858dc 100644 --- a/test/CodeGen/PowerPC/i32-to-float.ll +++ b/test/CodeGen/PowerPC/i32-to-float.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -29,6 +30,12 @@ entry: ; CHECK-A2: lfiwax [[REG:[0-9]+]], ; CHECK-A2: fcfids 1, [[REG]] ; CHECK-A2: blr + +; CHECK-VSX: @foo +; CHECK-VSX: stw 3, +; CHECK-VSX: lfiwax [[REG:[0-9]+]], +; CHECK-VSX: fcfids 1, [[REG]] +; CHECK-VSX: blr } define double @goo(i32 %a) nounwind { @@ -54,6 +61,12 @@ entry: ; CHECK-A2: lfiwax [[REG:[0-9]+]], ; CHECK-A2: fcfid 1, [[REG]] ; CHECK-A2: blr + +; CHECK-VSX: @goo +; CHECK-VSX: stw 3, +; CHECK-VSX: lfiwax [[REG:[0-9]+]], +; CHECK-VSX: xscvsxddp 1, [[REG]] +; CHECK-VSX: blr } define float @foou(i32 %a) nounwind { @@ -66,6 +79,12 @@ entry: ; CHECK-A2: lfiwzx [[REG:[0-9]+]], ; CHECK-A2: fcfidus 1, [[REG]] ; CHECK-A2: blr + +; CHECK-VSX: @foou +; CHECK-VSX: stw 3, +; CHECK-VSX: lfiwzx [[REG:[0-9]+]], +; CHECK-VSX: fcfidus 1, [[REG]] +; CHECK-VSX: blr } define double @goou(i32 %a) nounwind { @@ -78,5 +97,11 @@ entry: ; CHECK-A2: lfiwzx [[REG:[0-9]+]], ; CHECK-A2: fcfidu 1, [[REG]] ; CHECK-A2: blr + +; CHECK-VSX: @goou +; CHECK-VSX: stw 3, +; CHECK-VSX: lfiwzx [[REG:[0-9]+]], +; CHECK-VSX: xscvuxddp 1, [[REG]] +; CHECK-VSX: blr } diff --git a/test/CodeGen/PowerPC/i64-to-float.ll b/test/CodeGen/PowerPC/i64-to-float.ll index b81d109e7f4..025a875c190 100644 --- a/test/CodeGen/PowerPC/i64-to-float.ll +++ b/test/CodeGen/PowerPC/i64-to-float.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -12,6 +13,12 @@ entry: ; CHECK: lfd [[REG:[0-9]+]], ; CHECK: fcfids 1, [[REG]] ; CHECK: blr + +; CHECK-VSX: @foo +; CHECK-VSX: std 3, +; CHECK-VSX: lxsdx [[REG:[0-9]+]], +; CHECK-VSX: fcfids 1, [[REG]] +; CHECK-VSX: blr } define double @goo(i64 %a) nounwind { @@ -24,6 +31,12 @@ entry: ; CHECK: lfd [[REG:[0-9]+]], ; CHECK: fcfid 1, [[REG]] ; CHECK: blr + +; CHECK-VSX: @goo +; CHECK-VSX: std 3, +; CHECK-VSX: lxsdx [[REG:[0-9]+]], +; CHECK-VSX: xscvsxddp 1, [[REG]] +; CHECK-VSX: blr } define float @foou(i64 %a) nounwind { @@ -36,6 +49,12 @@ entry: ; CHECK: lfd [[REG:[0-9]+]], ; CHECK: fcfidus 1, [[REG]] ; CHECK: blr + +; CHECK-VSX: @foou +; CHECK-VSX: std 3, +; CHECK-VSX: lxsdx [[REG:[0-9]+]], +; CHECK-VSX: fcfidus 1, [[REG]] +; CHECK-VSX: blr } define double @goou(i64 %a) nounwind { @@ -48,5 +67,11 @@ entry: ; CHECK: lfd [[REG:[0-9]+]], ; CHECK: fcfidu 1, [[REG]] ; CHECK: blr + +; CHECK-VSX: @goou +; CHECK-VSX: std 3, +; CHECK-VSX: lxsdx [[REG:[0-9]+]], +; CHECK-VSX: xscvuxddp 1, [[REG]] +; CHECK-VSX: blr }