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https://github.com/c64scene-ar/llvm-6502.git
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For AArch64, lowering sext_inreg and generate optimized code by using SXTL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu
parent
38e6f7301d
commit
b6db372c96
@ -286,6 +286,15 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setExceptionSelectorRegister(AArch64::X1);
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if (Subtarget->hasNEON()) {
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v1i64, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v16i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
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@ -3574,7 +3583,25 @@ static bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) {
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return (Cnt >= 1 && Cnt <= ElementBits);
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}
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/// Checks for immediate versions of vector shifts and lowers them.
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static SDValue GenForSextInreg(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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EVT SrcVT, EVT DestVT, EVT SubRegVT,
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const int *Mask, SDValue Src) {
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SelectionDAG &DAG = DCI.DAG;
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SDValue Bitcast
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= DAG.getNode(ISD::BITCAST, SDLoc(N), SrcVT, Src);
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SDValue Sext
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= DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), DestVT, Bitcast);
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SDValue ShuffleVec
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= DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
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SDValue ExtractSubreg
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= SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N),
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SubRegVT, ShuffleVec,
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DAG.getTargetConstant(AArch64::sub_64, MVT::i32)), 0);
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return ExtractSubreg;
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}
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/// Checks for vector shifts and lowers them.
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static SDValue PerformShiftCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const AArch64Subtarget *ST) {
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@ -3583,6 +3610,51 @@ static SDValue PerformShiftCombine(SDNode *N,
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if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
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return PerformSRACombine(N, DCI);
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// We're looking for an SRA/SHL pair to help generating instruction
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// sshll v0.8h, v0.8b, #0
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// The instruction STXL is also the alias of this instruction.
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//
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// For example, for DAG like below,
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// v2i32 = sra (v2i32 (shl v2i32, 16)), 16
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// we can transform it into
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// v2i32 = EXTRACT_SUBREG
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// (v4i32 (suffle_vector
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// (v4i32 (sext (v4i16 (bitcast v2i32))),
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// undef, (0, 2, u, u)),
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// sub_64
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//
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// With this transformation we expect to generate "SSHLL + UZIP1"
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// Sometimes UZIP1 can be optimized away by combining with other context.
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int64_t ShrCnt, ShlCnt;
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if (N->getOpcode() == ISD::SRA
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&& (VT == MVT::v2i32 || VT == MVT::v4i16)
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&& isVShiftRImm(N->getOperand(1), VT, ShrCnt)
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&& N->getOperand(0).getOpcode() == ISD::SHL
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&& isVShiftRImm(N->getOperand(0).getOperand(1), VT, ShlCnt)) {
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SDValue Src = N->getOperand(0).getOperand(0);
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if (VT == MVT::v2i32 && ShrCnt == 16 && ShlCnt == 16) {
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// sext_inreg(v2i32, v2i16)
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// We essentially only care the Mask {0, 2, u, u}
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int Mask[4] = {0, 2, 4, 6};
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return GenForSextInreg(N, DCI, MVT::v4i16, MVT::v4i32, MVT::v2i32,
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Mask, Src);
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}
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else if (VT == MVT::v2i32 && ShrCnt == 24 && ShlCnt == 24) {
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// sext_inreg(v2i16, v2i8)
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// We essentially only care the Mask {0, u, 4, u, u, u, u, u, u, u, u, u}
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int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
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return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v2i32,
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Mask, Src);
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}
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else if (VT == MVT::v4i16 && ShrCnt == 8 && ShlCnt == 8) {
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// sext_inreg(v4i16, v4i8)
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// We essentially only care the Mask {0, 2, 4, 6, u, u, u, u, u, u, u, u}
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int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
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return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v4i16,
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Mask, Src);
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}
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}
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// Nothing to be done for scalar shifts.
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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if (!VT.isVector() || !TLI.isTypeLegal(VT))
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@ -1877,6 +1877,10 @@ def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b", USHLLvvi_16B, VPR
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def UXTL2vv_8H : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h", USHLLvvi_8H, VPR128, VPR128>;
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def UXTL2vv_4S : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s", USHLLvvi_4S, VPR128, VPR128>;
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def : Pat<(v8i16 (anyext (v8i8 VPR64:$Rn))), (USHLLvvi_8B VPR64:$Rn, 0)>;
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def : Pat<(v4i32 (anyext (v4i16 VPR64:$Rn))), (USHLLvvi_4H VPR64:$Rn, 0)>;
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def : Pat<(v2i64 (anyext (v2i32 VPR64:$Rn))), (USHLLvvi_2S VPR64:$Rn, 0)>;
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// Rounding/Saturating shift
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class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
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RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
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198
test/CodeGen/AArch64/sext_inreg.ll
Normal file
198
test/CodeGen/AArch64/sext_inreg.ll
Normal file
@ -0,0 +1,198 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; For formal arguments, we have the following vector type promotion,
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; v2i8 is promoted to v2i32(f64)
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; v2i16 is promoted to v2i32(f64)
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; v4i8 is promoted to v4i16(f64)
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; v8i1 is promoted to v8i16(f128)
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define <2 x i8> @test_sext_inreg_v2i8i16(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <2 x i8> %v1 to <2 x i16>
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%2 = sext <2 x i8> %v2 to <2 x i16>
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%3 = shufflevector <2 x i16> %1, <2 x i16> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i16> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <2 x i8> @test_sext_inreg_v2i8i16_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i16_2
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%a1 = shl <2 x i32> %v1, <i32 24, i32 24>
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%a2 = ashr <2 x i32> %a1, <i32 24, i32 24>
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%b1 = shl <2 x i32> %v2, <i32 24, i32 24>
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%b2 = ashr <2 x i32> %b1, <i32 24, i32 24>
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%c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
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%d = trunc <2 x i32> %c to <2 x i8>
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ret <2 x i8> %d
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}
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define <2 x i8> @test_sext_inreg_v2i8i32(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i32
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <2 x i8> %v1 to <2 x i32>
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%2 = sext <2 x i8> %v2 to <2 x i32>
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%3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i32> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <2 x i8> @test_sext_inreg_v2i8i64(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i64
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; CHECK: ushll v1.2d, v1.2s, #0
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; CHECK: ushll v0.2d, v0.2s, #0
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; CHECK: shl v0.2d, v0.2d, #56
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; CHECK: sshr v0.2d, v0.2d, #56
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; CHECK: shl v1.2d, v1.2d, #56
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; CHECK: sshr v1.2d, v1.2d, #56
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%1 = sext <2 x i8> %v1 to <2 x i64>
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%2 = sext <2 x i8> %v2 to <2 x i64>
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i64> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <4 x i8> @test_sext_inreg_v4i8i16(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <4 x i8> %v1 to <4 x i16>
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%2 = sext <4 x i8> %v2 to <4 x i16>
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%3 = shufflevector <4 x i16> %1, <4 x i16> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%4 = trunc <4 x i16> %3 to <4 x i8>
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ret <4 x i8> %4
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}
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define <4 x i8> @test_sext_inreg_v4i8i16_2(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i16_2
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%a1 = shl <4 x i16> %v1, <i16 8, i16 8, i16 8, i16 8>
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%a2 = ashr <4 x i16> %a1, <i16 8, i16 8, i16 8, i16 8>
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%b1 = shl <4 x i16> %v2, <i16 8, i16 8, i16 8, i16 8>
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%b2 = ashr <4 x i16> %b1, <i16 8, i16 8, i16 8, i16 8>
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%c = shufflevector <4 x i16> %a2, <4 x i16> %b2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%d = trunc <4 x i16> %c to <4 x i8>
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ret <4 x i8> %d
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}
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define <4 x i8> @test_sext_inreg_v4i8i32(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i32
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; CHECK: ushll v1.4s, v1.4h, #0
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; CHECK: ushll v0.4s, v0.4h, #0
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; CHECK: shl v0.4s, v0.4s, #24
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; CHECK: sshr v0.4s, v0.4s, #24
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; CHECK: shl v1.4s, v1.4s, #24
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; CHECK: sshr v1.4s, v1.4s, #24
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%1 = sext <4 x i8> %v1 to <4 x i32>
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%2 = sext <4 x i8> %v2 to <4 x i32>
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%4 = trunc <4 x i32> %3 to <4 x i8>
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ret <4 x i8> %4
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}
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define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v8i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK: sshll v1.8h, v1.8b, #0
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%1 = sext <8 x i8> %v1 to <8 x i16>
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%2 = sext <8 x i8> %v2 to <8 x i16>
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%4 = trunc <8 x i16> %3 to <8 x i8>
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ret <8 x i8> %4
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}
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define <8 x i1> @test_sext_inreg_v8i1i16(<8 x i1> %v1, <8 x i1> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v8i1i16
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; CHECK: ushll v1.8h, v1.8b, #0
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; CHECK: ushll v0.8h, v0.8b, #0
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; CHECK: shl v0.8h, v0.8h, #15
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; CHECK: sshr v0.8h, v0.8h, #15
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; CHECK: shl v1.8h, v1.8h, #15
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; CHECK: sshr v1.8h, v1.8h, #15
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%1 = sext <8 x i1> %v1 to <8 x i16>
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%2 = sext <8 x i1> %v2 to <8 x i16>
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%4 = trunc <8 x i16> %3 to <8 x i1>
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ret <8 x i1> %4
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}
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define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i32
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; CHECK: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
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%1 = sext <2 x i16> %v1 to <2 x i32>
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%2 = sext <2 x i16> %v2 to <2 x i32>
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%3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i32> %3 to <2 x i16>
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ret <2 x i16> %4
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}
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define <2 x i16> @test_sext_inreg_v2i16i32_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i32_2
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; CHECK: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
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%a1 = shl <2 x i32> %v1, <i32 16, i32 16>
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%a2 = ashr <2 x i32> %a1, <i32 16, i32 16>
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%b1 = shl <2 x i32> %v2, <i32 16, i32 16>
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%b2 = ashr <2 x i32> %b1, <i32 16, i32 16>
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%c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
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%d = trunc <2 x i32> %c to <2 x i16>
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ret <2 x i16> %d
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}
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define <2 x i16> @test_sext_inreg_v2i16i64(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i64
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; CHECK: ushll v1.2d, v1.2s, #0
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; CHECK: ushll v0.2d, v0.2s, #0
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; CHECK: shl v0.2d, v0.2d, #48
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; CHECK: sshr v0.2d, v0.2d, #48
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; CHECK: shl v1.2d, v1.2d, #48
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; CHECK: sshr v1.2d, v1.2d, #48
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%1 = sext <2 x i16> %v1 to <2 x i64>
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%2 = sext <2 x i16> %v2 to <2 x i64>
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
|
||||
%4 = trunc <2 x i64> %3 to <2 x i16>
|
||||
ret <2 x i16> %4
|
||||
}
|
||||
|
||||
define <4 x i16> @test_sext_inreg_v4i16i32(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
|
||||
; CHECK-LABEL: test_sext_inreg_v4i16i32
|
||||
; CHECK: sshll v0.4s, v0.4h, #0
|
||||
; CHECK: sshll v1.4s, v1.4h, #0
|
||||
%1 = sext <4 x i16> %v1 to <4 x i32>
|
||||
%2 = sext <4 x i16> %v2 to <4 x i32>
|
||||
%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%4 = trunc <4 x i32> %3 to <4 x i16>
|
||||
ret <4 x i16> %4
|
||||
}
|
||||
|
||||
define <2 x i32> @test_sext_inreg_v2i32i64(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
|
||||
; CHECK-LABEL: test_sext_inreg_v2i32i64
|
||||
; CHECK: sshll v0.2d, v0.2s, #0
|
||||
; CHECK: sshll v1.2d, v1.2s, #0
|
||||
%1 = sext <2 x i32> %v1 to <2 x i64>
|
||||
%2 = sext <2 x i32> %v2 to <2 x i64>
|
||||
%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
|
||||
%4 = trunc <2 x i64> %3 to <2 x i32>
|
||||
ret <2 x i32> %4
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user