6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-26 05:32:25 +00:00
Code Issues Projects Releases Wiki Activity

PR9838: Fix transform introduced in r127064 to not trigger when only one side of the icmp is an exact shift.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-05-05 21:59:18 +00:00
parent 108709d4d1
commit b6e7cd655c
3 changed files with 13 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Analysis/InstructionSimplify.cpp
View File

@ -1847,7 +1847,7 @@ static Value *SimplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS,
// fall-through
case Instruction::SDiv:
case Instruction::AShr:
if (!LBO->isExact() && !RBO->isExact())
if (!LBO->isExact() || !RBO->isExact())
break;
if (Value *V = SimplifyICmpInst(Pred, LBO->getOperand(0),
RBO->getOperand(0), TD, DT, MaxRecurse-1))

2
lib/Transforms/InstCombine/InstCombineCompares.cpp
View File

@ -2400,7 +2400,7 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {
// fall-through
case Instruction::SDiv:
case Instruction::AShr:
if (!BO0->isExact() && !BO1->isExact())
if (!BO0->isExact() || !BO1->isExact())
break;
return new ICmpInst(I.getPredicate(), BO0->getOperand(0),
BO1->getOperand(0));

11
test/Transforms/InstCombine/icmp.ll
View File

@ -510,3 +510,14 @@ define i1 @test52(i32 %x1) nounwind {
ret i1 %A
}
; PR9838
; CHECK: @test53
; CHECK-NEXT: ashr exact
; CHECK-NEXT: ashr
; CHECK-NEXT: icmp
define i1 @test53(i32 %a, i32 %b) nounwind {
%x = ashr exact i32 %a, 30
%y = ashr i32 %b, 30
%z = icmp eq i32 %x, %y
ret i1 %z
}