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Multiclassify the LDR/STR encoding patterns. The only functionality difference
is the addition of the FoldableAsLoad & Rematerializable flags to some of the load instructions. ARM has these flags set for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
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Bill Wendling
parent
bbc726d624
commit
b6faf65215
@ -606,42 +606,59 @@ def tTRAP : TI<(outs), (ins), IIC_Br,
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// Load Store Instructions.
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//
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// Loads: reg/reg and reg/imm5
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def tLDRr : // A8.6.60
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T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_rrs4:$addr),
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AddrModeT1_4, IIC_iLoad_r,
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"ldr", "\t$Rt, $addr",
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[(set tGPR:$Rt, (load t_addrmode_rrs4:$addr))]>;
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multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
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Operand AddrMode_r, Operand AddrMode_i,
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AddrMode am, InstrItinClass itin_r,
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InstrItinClass itin_i, string asm,
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PatFrag opnode> {
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def r :
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T1pILdStEncode<reg_opc,
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(outs tGPR:$Rt), (ins AddrMode_r:$addr),
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am, itin_r, asm, "\t$Rt, $addr",
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[(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
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def i :
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T1pILdStEncodeImm<imm_opc, 1 /* Load */,
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(outs tGPR:$Rt), (ins AddrMode_i:$addr),
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am, itin_i, asm, "\t$Rt, $addr",
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[(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
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}
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// Stores: reg/reg and reg/imm5
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multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
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Operand AddrMode_r, Operand AddrMode_i,
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AddrMode am, InstrItinClass itin_r,
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InstrItinClass itin_i, string asm,
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PatFrag opnode> {
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def r :
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T1pILdStEncode<reg_opc,
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(outs), (ins tGPR:$Rt, AddrMode_r:$addr),
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am, itin_r, asm, "\t$Rt, $addr",
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[(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
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def i :
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T1pILdStEncodeImm<imm_opc, 0 /* Store */,
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(outs), (ins tGPR:$Rt, AddrMode_i:$addr),
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am, itin_i, asm, "\t$Rt, $addr",
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[(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
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}
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def tLDRi : // A8.6.57
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T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_is4:$addr),
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AddrModeT1_4, IIC_iLoad_i,
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"ldr", "\t$Rt, $addr",
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[(set tGPR:$Rt, (load t_addrmode_is4:$addr))]>;
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// A8.6.57 & A8.6.60
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defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
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t_addrmode_is4, AddrModeT1_4,
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IIC_iLoad_r, IIC_iLoad_i, "ldr",
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UnOpFrag<(load node:$Src)>>;
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def tLDRBr : // A8.6.64
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T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_rrs1:$addr),
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AddrModeT1_1, IIC_iLoad_bh_r,
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"ldrb", "\t$Rt, $addr",
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[(set tGPR:$Rt, (zextloadi8 t_addrmode_rrs1:$addr))]>;
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// A8.6.64 & A8.6.61
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defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
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t_addrmode_is1, AddrModeT1_1,
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IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
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UnOpFrag<(zextloadi8 node:$Src)>>;
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def tLDRBi : // A8.6.61
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T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_is1:$addr),
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AddrModeT1_1, IIC_iLoad_bh_i,
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"ldrb", "\t$Rt, $addr",
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[(set tGPR:$Rt, (zextloadi8 t_addrmode_is1:$addr))]>;
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def tLDRHr : // A8.6.76
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T1pILdStEncode<0b101, (outs tGPR:$Rt), (ins t_addrmode_rrs2:$addr),
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AddrModeT1_2, IIC_iLoad_bh_r,
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"ldrh", "\t$Rt, $addr",
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[(set tGPR:$Rt, (zextloadi16 t_addrmode_rrs2:$addr))]>;
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def tLDRHi : // A8.6.73
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T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_is2:$addr),
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AddrModeT1_2, IIC_iLoad_bh_i,
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"ldrh", "\t$Rt, $addr",
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[(set tGPR:$Rt, (zextloadi16 t_addrmode_is2:$addr))]>;
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// A8.6.76 & A8.6.73
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defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
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t_addrmode_is2, AddrModeT1_2,
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IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
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UnOpFrag<(zextloadi16 node:$Src)>>;
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let AddedComplexity = 10 in
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def tLDRSB : // A8.6.80
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@ -703,41 +720,24 @@ def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
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let Inst{7-0} = addr;
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}
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def tSTRr : // A8.6.194
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T1pILdStEncode<0b000, (outs), (ins tGPR:$Rt, t_addrmode_rrs4:$addr),
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AddrModeT1_4, IIC_iStore_r,
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"str", "\t$Rt, $addr",
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[(store tGPR:$Rt, t_addrmode_rrs4:$addr)]>;
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// A8.6.194 & A8.6.192
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defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
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t_addrmode_is4, AddrModeT1_4,
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IIC_iStore_r, IIC_iStore_i, "str",
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BinOpFrag<(store node:$LHS, node:$RHS)>>;
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def tSTRi : // A8.6.192
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T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_is4:$addr),
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AddrModeT1_4, IIC_iStore_i,
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"str", "\t$Rt, $addr",
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[(store tGPR:$Rt, t_addrmode_is4:$addr)]>;
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// A8.6.197 & A8.6.195
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defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
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t_addrmode_is1, AddrModeT1_1,
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IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
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BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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def tSTRBr : // A8.6.197
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T1pILdStEncode<0b010, (outs), (ins tGPR:$Rt, t_addrmode_rrs1:$addr),
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AddrModeT1_1, IIC_iStore_bh_r,
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"strb", "\t$Rt, $addr",
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[(truncstorei8 tGPR:$Rt, t_addrmode_rrs1:$addr)]>;
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// A8.6.207 & A8.6.205
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defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
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t_addrmode_is2, AddrModeT1_2,
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IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
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BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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def tSTRBi : // A8.6.195
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T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_is1:$addr),
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AddrModeT1_1, IIC_iStore_bh_i,
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"strb", "\t$Rt, $addr",
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[(truncstorei8 tGPR:$Rt, t_addrmode_is1:$addr)]>;
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def tSTRHr : // A8.6.207
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T1pILdStEncode<0b001, (outs), (ins tGPR:$Rt, t_addrmode_rrs2:$addr),
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AddrModeT1_2, IIC_iStore_bh_r,
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"strh", "\t$Rt, $addr",
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[(truncstorei16 tGPR:$Rt, t_addrmode_rrs2:$addr)]>;
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def tSTRHi : // A8.6.205
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T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_is2:$addr),
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AddrModeT1_2, IIC_iStore_bh_i,
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"strh", "\t$Rt, $addr",
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[(truncstorei16 tGPR:$Rt, t_addrmode_is2:$addr)]>;
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def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
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"str", "\t$Rt, $addr",
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