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This patch is another step in the direction of adding vector select. In this
patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1597,6 +1597,13 @@ private:
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const TargetData *TD;
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const TargetLoweringObjectFile &TLOF;
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/// We are in the process of implementing a new TypeLegalization action
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/// which is the promotion of vector elements. This feature is under
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/// development. Until this feature is complete, it is only enabled using a
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/// flag. We pass this flag using a member because of circular dep issues.
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/// This member will be removed with the flag once we complete the transition.
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bool mayPromoteElements;
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/// PointerTy - The type to use for pointers, usually i32 or i64.
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///
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MVT PointerTy;
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@ -1756,10 +1763,10 @@ private:
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EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
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LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT());
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assert((NVT.isSimple() && LA != TypeLegal )?
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ValueTypeActions.getTypeAction(
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NVT.getSimpleVT()) != TypePromoteInteger
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: 1 && "Promote may not follow Expand or Promote");
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assert(
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(!(NVT.isSimple() && LA != TypeLegal) ||
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ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger)
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&& "Promote may not follow Expand or Promote");
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return LegalizeKind(LA, NVT);
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}
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@ -1791,6 +1798,51 @@ private:
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if (NumElts == 1)
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return LegalizeKind(TypeScalarizeVector, EltVT);
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// If we allow the promotion of vector elements using a flag,
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// then try to widen vector elements until a legal type is found.
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if (mayPromoteElements && EltVT.isInteger()) {
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// Vectors with a number of elements that is not a power of two are always
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// widened, for example <3 x float> -> <4 x float>.
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if (!VT.isPow2VectorType()) {
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NumElts = (unsigned)NextPowerOf2(NumElts);
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EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
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return LegalizeKind(TypeWidenVector, NVT);
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}
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// Examine the element type.
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LegalizeKind LK = getTypeConversion(Context, EltVT);
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// If type is to be expanded, split the vector.
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// <4 x i140> -> <2 x i140>
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if (LK.first == TypeExpandInteger)
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return LegalizeKind(TypeSplitVector,
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EVT::getVectorVT(Context, EltVT, NumElts / 2));
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// Promote the integer element types until a legal vector type is found
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// or until the element integer type is too big. If a legal type was not
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// found, fallback to the usual mechanism of widening/splitting the
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// vector.
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while (1) {
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// Increase the bitwidth of the element to the next pow-of-two
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// (which is greater than 8 bits).
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EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
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).getRoundIntegerType(Context);
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// Stop trying when getting a non-simple element type.
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// Note that vector elements may be greater than legal vector element
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// types. Example: X86 XMM registers hold 64bit element on 32bit systems.
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if (!EltVT.isSimple()) break;
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// Build a new vector type and check if it is legal.
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MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
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// Found a legal promoted vector type.
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if (ValueTypeActions.getTypeAction(NVT) == TypeLegal)
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return LegalizeKind(TypePromoteInteger,
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EVT::getVectorVT(Context, EltVT, NumElts));
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}
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}
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// Try to widen the vector until a legal type is found.
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// If there is no wider legal type, split the vector.
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while (1) {
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@ -26,11 +26,19 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <cctype>
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using namespace llvm;
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/// We are in the process of implementing a new TypeLegalization action
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/// - the promotion of vector elements. This feature is disabled by default
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/// and only enabled using this flag.
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static cl::opt<bool>
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AllowPromoteIntElem("promote-elements", cl::Hidden,
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cl::desc("Allow promotion of integer vector element types"));
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namespace llvm {
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TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
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bool isLocal = GV->hasLocalLinkage();
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@ -528,7 +536,8 @@ static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
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/// NOTE: The constructor takes ownership of TLOF.
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TargetLowering::TargetLowering(const TargetMachine &tm,
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const TargetLoweringObjectFile *tlof)
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: TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
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: TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
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mayPromoteElements(AllowPromoteIntElem) {
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// All operations default to being supported.
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memset(OpActions, 0, sizeof(OpActions));
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memset(LoadExtActions, 0, sizeof(LoadExtActions));
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@ -814,6 +823,24 @@ void TargetLowering::computeRegisterProperties() {
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bool IsLegalWiderType = false;
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for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
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EVT SVT = (MVT::SimpleValueType)nVT;
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// If we allow the promotion of vector elements using a flag,
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// then return TypePromoteInteger on vector elements.
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if (mayPromoteElements) {
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// Promote vectors of integers to vectors with the same number
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// of elements, with a wider element type.
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if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
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&& SVT.getVectorNumElements() == NElts &&
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isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
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TransformToType[i] = SVT;
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RegisterTypeForVT[i] = SVT;
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NumRegistersForVT[i] = 1;
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ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
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IsLegalWiderType = true;
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break;
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}
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}
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if (SVT.getVectorElementType() == EltVT &&
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SVT.getVectorNumElements() > NElts &&
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isTypeLegal(SVT)) {
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15
test/CodeGen/Generic/promote-integers.ll
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15
test/CodeGen/Generic/promote-integers.ll
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@ -0,0 +1,15 @@
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; Test that vectors are scalarized/lowered correctly.
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; RUN: llc -march=x86 -promote-elements < %s | FileCheck %s
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; This test is the poster-child for integer-element-promotion.
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; Until this feature is complete, we mark this test as expected to fail.
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; XFAIL: *
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; CHECK: vector_code
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; CHECK: ret
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define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 ) {
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%C = icmp eq <4 x i64> %A, %B
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%K = xor <4 x i1> <i1 1, i1 1, i1 1, i1 1>, %C
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%D = select <4 x i1> %K, <4 x float> %R1, <4 x float> %R0
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ret <4 x float> %D
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}
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