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Allocate SystemZ callee-saved registers backwards: R13-R6

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The reserved R14-R15 are always saved in the prolog, and using CSRs
starting from R13 allows them to be saved in one instruction.

Thanks to Anton for explaining this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133233 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-17 03:47:30 +00:00
parent f3a789d931
commit b712ef9569
1 changed files with 13 additions and 7 deletions
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20
lib/Target/SystemZ/SystemZRegisterInfo.td
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@@ -161,13 +161,17 @@ def F15L : FPRL<15, "f15", [F15S]>;
// Status register // Status register
def PSW : SystemZReg<"psw">; def PSW : SystemZReg<"psw">;
/// Register classes /// Register classes.
def GR32 : RegisterClass<"SystemZ", [i32], 32, (sequence "R%uW", 0, 15)>; /// Allocate the callee-saved R6-R12 backwards. That way they can be saved
/// together with R14 and R15 in one prolog instruction.
def GR32 : RegisterClass<"SystemZ", [i32], 32, (add (sequence "R%uW", 0, 5),
(sequence "R%uW", 15, 6))>;
/// Registers used to generate address. Everything except R0. /// Registers used to generate address. Everything except R0.
def ADDR32 : RegisterClass<"SystemZ", [i32], 32, (sub GR32, R0W)>; def ADDR32 : RegisterClass<"SystemZ", [i32], 32, (sub GR32, R0W)>;
def GR64 : RegisterClass<"SystemZ", [i64], 64, (sequence "R%uD", 0, 15)> { def GR64 : RegisterClass<"SystemZ", [i64], 64, (add (sequence "R%uD", 0, 5),
(sequence "R%uD", 15, 6))> {
let SubRegClasses = [(GR32 subreg_32bit)]; let SubRegClasses = [(GR32 subreg_32bit)];
} }
@@ -176,13 +180,15 @@ def ADDR64 : RegisterClass<"SystemZ", [i64], 64, (sub GR64, R0D)> {
} }
// Even-odd register pairs // Even-odd register pairs
def GR64P : RegisterClass<"SystemZ", [v2i32], 64, (add R0P, R2P, R4P, R6P, R8P, def GR64P : RegisterClass<"SystemZ", [v2i32], 64, (add R0P, R2P, R4P,
R10P, R12P, R14P)> { R12P, R10P, R8P, R6P,
R14P)> {
let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)]; let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)];
} }
def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q, R6Q, R8Q, def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q,
R10Q, R12Q, R14Q)> { R12Q, R10Q, R8Q, R6Q,
R14Q)> {
let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32), let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32),
(GR64 subreg_even, subreg_odd)]; (GR64 subreg_even, subreg_odd)];
} }