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s/Method/Function

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2180 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-04-08 22:03:57 +00:00
parent 75cf7cf00d
commit b7653df085
19 changed files with 73 additions and 77 deletions
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4
lib/CodeGen/InstrSched/InstrScheduling.cpp
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@@ -1504,13 +1504,13 @@ namespace {
Destroyed.push_back(MethodLiveVarInfo::ID);
}
bool runOnMethod(Method *M);
bool runOnMethod(Function *F);
};
} // end anonymous namespace
bool
InstructionSchedulingWithSSA::runOnMethod(Method *M)
InstructionSchedulingWithSSA::runOnMethod(Function *M)
{
if (SchedDebugLevel == Sched_Disable)
return false;

2
lib/CodeGen/InstrSched/SchedPriorities.cpp
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@@ -25,7 +25,7 @@
#include <iostream>
using std::cerr;
SchedPriorities::SchedPriorities(const Method *method, const SchedGraph *G,
SchedPriorities::SchedPriorities(const Function *, const SchedGraph *G,
MethodLiveVarInfo &LVI)
: curTime(0), graph(G), methodLiveVarInfo(LVI),
nodeDelayVec(G->getNumNodes(), INVALID_LATENCY), // make errors obvious

6
lib/CodeGen/RegAlloc/PhyRegAlloc.h
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@@ -62,7 +62,7 @@ typedef std::hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
//----------------------------------------------------------------------------
// class PhyRegAlloc:
// Main class the register allocator. Call allocateRegisters() to allocate
// registers for a Method.
// registers for a Function.
//----------------------------------------------------------------------------
@@ -70,7 +70,7 @@ class PhyRegAlloc: public NonCopyable {
std::vector<RegClass *> RegClassList; // vector of register classes
const TargetMachine &TM; // target machine
const Method* Meth; // name of the method we work on
const Function *Meth; // name of the function we work on
MachineCodeForMethod &mcInfo; // descriptor for method's native code
MethodLiveVarInfo *const LVI; // LV information for this method
// (already computed for BBs)
@@ -85,7 +85,7 @@ class PhyRegAlloc: public NonCopyable {
// currently not used
public:
PhyRegAlloc(Method *M, const TargetMachine& TM, MethodLiveVarInfo *Lvi,
PhyRegAlloc(Function *F, const TargetMachine& TM, MethodLiveVarInfo *Lvi,
cfg::LoopInfo *LoopDepthCalc);
~PhyRegAlloc();

15
lib/CodeGen/RegAlloc/RegClass.h
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@@ -36,7 +36,7 @@ typedef std::vector<unsigned> ReservedColorListType;
//
//-----------------------------------------------------------------------------
class RegClass {
const Method *const Meth; // Method we are working on
const Function *const Meth; // Function we are working on
const MachineRegClassInfo *const MRC; // corresponding MRC
const unsigned RegClassID; // my int ID
@@ -47,7 +47,7 @@ class RegClass {
const ReservedColorListType *const ReservedColorList;
//
// for passing registers that are pre-allocated and cannot be used by the
// register allocator for this method.
// register allocator for this function.
bool *IsColorUsedArr;
//
@@ -69,14 +69,13 @@ class RegClass {
public:
RegClass(const Method *const M,
const MachineRegClassInfo *const MRC,
const ReservedColorListType *const RCL = NULL);
RegClass(const Function *M,
const MachineRegClassInfo *MRC,
const ReservedColorListType *RCL = 0);
~RegClass() { delete[] IsColorUsedArr; };
~RegClass() { delete[] IsColorUsedArr; }
inline void createInterferenceGraph()
{ IG.createGraph(); }
inline void createInterferenceGraph() { IG.createGraph(); }
inline InterferenceGraph &getIG() { return IG; }