6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-04 05:31:51 +00:00
Code Issues Projects Releases Wiki Activity

Be a little more specific about what is begin generated. Only print

Browse Source 
command line if VERBOSE=1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8453 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-09-10 19:52:54 +00:00
parent b3aad5d28f
commit b787e13e73
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
lib/Target/X86/Makefile
View File

@ -8,28 +8,28 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenInstrInfo.inc X86GenInstrSelector.inc
X86GenRegisterNames.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
@echo "Building $< register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
@echo "Building $< register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
@echo "Building $< register information implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
@echo "Building $< instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
@echo "Building $< instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
@echo "Tblgen'ing $<"
$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
@echo "Building $< instruction selector with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
clean::
$(VERB) rm -f *.inc