6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-10-25 10:27:04 +00:00
Code Issues Projects Releases Wiki Activity

Add a dagcombine optimization to convert concat_vectors of undefs into a single undef.

Browse Source 
The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
2012-07-14 21:30:27 +00:00
parent 27982e1108
commit b7e230d999
2 changed files with 28 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
test/CodeGen/X86/2012-07-10-shufnorm.ll Normal file
View File

@@ -0,0 +1,17 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx | FileCheck %s
; CHECK: ocl
define void @ocl() {
entry:
%vext = shufflevector <2 x double> zeroinitializer, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%vecinit = shufflevector <8 x double> %vext, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%vecinit1 = insertelement <8 x double> %vecinit, double undef, i32 2
%vecinit3 = insertelement <8 x double> %vecinit1, double undef, i32 3
%vecinit5 = insertelement <8 x double> %vecinit3, double 0.000000e+00, i32 4
%vecinit9 = shufflevector <8 x double> %vecinit5, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 9, i32 10>
store <8 x double> %vecinit9, <8 x double>* undef
ret void
; CHECK: vxorps
; CHECK: ret
}