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Several fixes and enhancements to the PPC32 backend.

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1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16826 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2004-10-07 22:30:03 +00:00
parent cb90de37a7
commit b816f0298d
3 changed files with 158 additions and 151 deletions
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3
lib/Target/PowerPC/PPC64ISelSimple.cpp
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@@ -1664,8 +1664,9 @@ void PPC64ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
static const unsigned OpcodeTab[] = {
PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
};
// FIXME: Convert this to the version from PPC32ISel
static const unsigned ImmOpcodeTab[] = {
PPC::ADDI, PPC::SUBI, PPC::ANDIo, PPC::ORI, PPC::XORI
PPC::ADDI, PPC::ADDI, PPC::ANDIo, PPC::ORI, PPC::XORI
};
static const unsigned RImmOpcodeTab[] = {
PPC::ADDI, PPC::SUBFIC, PPC::ANDIo, PPC::ORI, PPC::XORI