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ARM case-insensitive checking for APSR_nzcv.

Browse Source 
rdar://11056591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2012-03-15 21:34:14 +00:00
parent ccaea7dc0b
commit b84ad4aa7d
7 changed files with 37 additions and 10 deletions
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2
test/CodeGen/ARM/fpcmp-opt.ll
View File

@@ -9,7 +9,7 @@ entry:
; CHECK: vldr [[S0:s[0-9]+]],
; CHECK: vldr [[S1:s[0-9]+]],
; CHECK: vcmpe.f32 [[S1]], [[S0]]
; CHECK: vmrs apsr_nzcv, fpscr
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: beq
%0 = load float* %a
%1 = load float* %b

2
test/CodeGen/ARM/fpcmp_ueq.ll
View File

@@ -5,7 +5,7 @@ define i32 @f7(float %a, float %b) {
entry:
; CHECK: f7:
; CHECK: vcmpe.f32
; CHECK: vmrs apsr_nzcv, fpscr
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: movweq
; CHECK-NOT: vmrs
; CHECK: movwvs

4
test/CodeGen/ARM/ifcvt11.ll
View File

@@ -18,7 +18,7 @@ bb.nph: ; preds = %entry
bb: ; preds = %bb4, %bb.nph
; CHECK: vcmpe.f64
; CHECK: vmrs apsr_nzcv, fpscr
; CHECK: vmrs APSR_nzcv, fpscr
%r.19 = phi i32 [ 0, %bb.nph ], [ %r.0, %bb4 ]
%n.08 = phi i32 [ 0, %bb.nph ], [ %10, %bb4 ]
%scevgep10 = getelementptr inbounds %struct.xyz_t* %p, i32 %n.08, i32 0
@@ -33,7 +33,7 @@ bb1: ; preds = %bb
; CHECK-NOT: vcmpemi
; CHECK-NOT: vmrsmi
; CHECK: vcmpe.f64
; CHECK: vmrs apsr_nzcv, fpscr
; CHECK: vmrs APSR_nzcv, fpscr
%scevgep12 = getelementptr %struct.xyz_t* %p, i32 %n.08, i32 2
%6 = load double* %scevgep12, align 4
%7 = fcmp uge double %3, %6