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R600/SI: Handle REG_SEQUENCE in fitsRegClass()

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-06-03 17:39:54 +00:00
parent 051a28e0e8
commit b89a467559
1 changed files with 13 additions and 3 deletions
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16
lib/Target/R600/SIISelLowering.cpp
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@ -523,10 +523,20 @@ bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
if (OpClassID == -1)
OpClass = getRegClassFor(Op.getSimpleValueType());
else
if (OpClassID == -1) {
switch (MN->getMachineOpcode()) {
case AMDGPU::REG_SEQUENCE:
// Operand 0 is the register class id for REG_SEQUENCE instructions.
OpClass = TRI->getRegClass(
cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue());
break;
default:
OpClass = getRegClassFor(Op.getSimpleValueType());
break;
}
} else {
OpClass = TRI->getRegClass(OpClassID);
}
} else if (Node->getOpcode() == ISD::CopyFromReg) {
RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());