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[mips][mips64r6] Add compact branch instructions
Differential Revision: http://reviews.llvm.org/D3691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208974 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
parent
0885a28635
commit
b8c3bcbbfa
@ -205,6 +205,16 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder);
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// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
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// shifted left by 1 bit.
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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@ -856,6 +866,26 @@ static DecodeStatus DecodeJumpTarget(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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const void *Decoder) {
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int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
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Inst.addOperand(MCOperand::CreateImm(BranchOffset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
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unsigned Offset,
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uint64_t Address,
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@ -242,6 +242,46 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
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return 0;
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}
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/// getBranchTarget21OpValue - Return binary encoding of the branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 4.
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if (MO.isImm()) return MO.getImm() >> 2;
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assert(MO.isExpr() &&
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"getBranchTarget21OpValue expects only expressions or immediates");
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// TODO: Push 21 PC fixup.
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return 0;
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}
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/// getBranchTarget26OpValue - Return binary encoding of the branch
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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unsigned MipsMCCodeEmitter::
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getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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// If the destination is an immediate, divide by 4.
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if (MO.isImm()) return MO.getImm() >> 2;
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assert(MO.isExpr() &&
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"getBranchTarget26OpValue expects only expressions or immediates");
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// TODO: Push 26 PC fixup.
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return 0;
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}
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/// getJumpTargetOpValue - Return binary encoding of the jump
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/// target operand. If the machine operand requires relocation,
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/// record the relocation and return zero.
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@ -88,6 +88,20 @@ public:
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getBranchTarget21OpValue - Return binary encoding of the branch
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// offset operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getBranchTarget26OpValue - Return binary encoding of the branch
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// offset operand. If the machine operand requires relocation,
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// record the relocation and return zero.
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unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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// getMachineOpValue - Return binary encoding of operand. If the machin
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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@ -191,6 +191,42 @@ class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
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let Inst{5-0} = funct;
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}
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class CMP_BRANCH_OFF16_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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class CMP_BRANCH_RT_OFF16_FM<bits<6> funct> : CMP_BRANCH_OFF16_FM<funct> {
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let Inst{25-21} = 0b00000;
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}
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class CMP_BRANCH_OFF21_FM<bits<6> funct> : MipsR6Inst {
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bits<5> rs;
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bits<21> offset;
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bits<32> Inst;
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let Inst{31-26} = funct;
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let Inst{25-21} = rs;
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let Inst{20-0} = offset;
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}
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class BRANCH_OFF26_FM<bits<6> funct> : MipsR6Inst {
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bits<32> Inst;
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bits<26> offset;
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let Inst{31-26} = funct;
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let Inst{25-0} = offset;
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}
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class SPECIAL3_ALIGN_FM<OPCODE6 Operation> : MipsR6Inst {
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bits<5> rd;
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bits<5> rs;
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@ -52,6 +52,20 @@ include "Mips32r6InstrFormats.td"
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// Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
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// Rencoded: [ls][wd]c2
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def brtarget21 : Operand<OtherVT> {
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let EncoderMethod = "getBranchTarget21OpValue";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget21";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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def brtarget26 : Operand<OtherVT> {
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let EncoderMethod = "getBranchTarget26OpValue";
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let OperandType = "OPERAND_PCREL";
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let DecoderMethod = "DecodeBranchTarget26";
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let ParserMatchClass = MipsJumpTargetAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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@ -63,6 +77,21 @@ class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
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class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
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class AUI_ENC : AUI_FM;
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class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
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class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
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class BC_ENC : BRANCH_OFF26_FM<0b110010>;
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class BEQC_ENC : CMP_BRANCH_OFF16_FM<0b001000>;
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class BNEC_ENC : CMP_BRANCH_OFF16_FM<0b011000>;
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class BLTZC_ENC : CMP_BRANCH_OFF16_FM<0b010111>;
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class BGEZC_ENC : CMP_BRANCH_OFF16_FM<0b010110>;
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class BLEZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010110>;
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class BGTZC_ENC : CMP_BRANCH_RT_OFF16_FM<0b010111>;
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class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
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class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
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class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
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class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
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class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
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@ -215,6 +244,66 @@ class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
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class BRANCH_DESC_BASE {
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bit isBranch = 1;
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bit isTerminator = 1;
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bit hasDelaySlot = 0;
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}
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class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$offset");
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bit isBarrier = 1;
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}
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class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
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list<Register> Defs = [AT];
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}
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class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
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list<Register> Defs = [AT];
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}
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class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
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RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
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dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
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list<Register> Defs = [AT];
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}
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class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
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class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
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class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
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class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd> {
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string Constraints = "$rs = $rt";
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}
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class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd> {
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string Constraints = "$rs = $rt";
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}
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class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
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class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
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class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
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class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
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class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rt);
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@ -316,31 +405,31 @@ def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
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def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
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def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
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def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
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def BALC;
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def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
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def BC1EQZ;
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def BC1NEZ;
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def BC2EQZ;
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def BC2NEZ;
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def BC;
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def BEQC;
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def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
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def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
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def BEQZALC;
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def BEQZC;
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def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
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def BGEC; // Also aliased to blec with operands swapped
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def BGEUC; // Also aliased to bleuc with operands swapped
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def BGEZALC;
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def BGEZC;
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def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
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def BGTZALC;
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def BGTZC;
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def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
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def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
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def BLEZALC;
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def BLEZC;
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def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
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def BLTC; // Also aliased to bgtc with operands swapped
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def BLTUC; // Also aliased to bgtuc with operands swapped
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def BLTZALC;
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def BLTZC;
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def BNEC;
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def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
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def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
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def BNEZALC;
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def BNEZC;
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def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
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def BNVC;
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def BOVC;
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def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
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@ -110,6 +110,11 @@ private:
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unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTarget21OpValue(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTarget26OpValue(const MachineInstr &MI,
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unsigned OpNo) const;
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
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@ -203,6 +208,18 @@ unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI,
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTarget21OpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTarget26OpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
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unsigned OpNo) const {
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MachineOperand MO = MI.getOperand(OpNo);
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@ -9,6 +9,16 @@
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
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aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
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auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
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balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
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bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
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beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
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bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
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beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90]
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bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90]
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bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40]
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bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40]
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blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40]
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bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40]
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bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
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cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
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cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
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@ -9,6 +9,16 @@
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38]
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aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9]
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auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff]
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balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8]
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bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8]
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beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
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bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40]
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beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90]
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bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90]
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bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40]
|
||||
bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40]
|
||||
blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40]
|
||||
bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40]
|
||||
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20]
|
||||
cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80]
|
||||
cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user