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Add Cortex-A53 and Cortex-A57 cores to the AArch64 backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201305 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,8 +36,19 @@ def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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include "AArch64Schedule.td"
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include "AArch64Schedule.td"
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Processor<"generic", GenericItineraries, [FeatureFPARMv8]>;
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def : Processor<"generic", GenericItineraries, [FeatureFPARMv8]>;
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def : ProcNoItin<"cortex-a53", [FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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def : ProcNoItin<"cortex-a57", [FeatureFPARMv8,
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FeatureNEON,
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FeatureCrypto]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register File Description
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// Register File Description
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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13
test/CodeGen/AArch64/cpus.ll
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13
test/CodeGen/AArch64/cpus.ll
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@ -0,0 +1,13 @@
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; This tests that llc accepts all valid AArch64 CPUs
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; RUN: llc < %s -march=aarch64 -mcpu=generic 2>&1 | FileCheck %s
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; RUN: llc < %s -march=aarch64 -mcpu=cortex-a53 2>&1 | FileCheck %s
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; RUN: llc < %s -march=aarch64 -mcpu=cortex-a57 2>&1 | FileCheck %s
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; RUN: llc < %s -march=aarch64 -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
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; CHECK-NOT: {{.*}} is not a recognized processor for this target
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; INVALID: {{.*}} is not a recognized processor for this target
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define i32 @f(i64 %z) {
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ret i32 0
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}
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