diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index a8a519a5ec3..72f40a017b4 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -30,16 +30,6 @@ static cl::opt EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")); -static inline -const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { - return MIB.addImm((int64_t)ARMCC::AL).addReg(0); -} - -static inline -const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { - return MIB.addReg(0); -} - ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI) : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) { } diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index c300264c822..1b0ef21fbae 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -14,9 +14,10 @@ #ifndef ARMBASEINSTRUCTIONINFO_H #define ARMBASEINSTRUCTIONINFO_H -#include "llvm/Target/TargetInstrInfo.h" -#include "ARMRegisterInfo.h" #include "ARM.h" +#include "ARMRegisterInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetInstrInfo.h" namespace llvm { class ARMSubtarget; @@ -187,6 +188,16 @@ namespace ARMII { }; } +static inline +const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { + return MIB.addImm((int64_t)ARMCC::AL).addReg(0); +} + +static inline +const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { + return MIB.addReg(0); +} + class ARMBaseInstrInfo : public TargetInstrInfoImpl { protected: // Can be only subclassed. diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index 356e2e2c50a..ddc6e0d154a 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -22,11 +22,6 @@ using namespace llvm; -static inline -const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { - return MIB.addImm((int64_t)ARMCC::AL).addReg(0); -} - Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI), RI(*this, STI) { } diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 9c933063230..e2c511a849f 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -47,16 +47,6 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, : ARMBaseRegisterInfo(tii, sti) { } -static inline -const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { - return MIB.addImm((int64_t)ARMCC::AL).addReg(0); -} - -static inline -const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { - return MIB.addReg(ARM::CPSR); -} - /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 6103463e87b..081cf4f5503 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -87,3 +87,24 @@ Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { return false; } + +bool +Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (I != MBB.end()) DL = I->getDebugLoc(); + + if ((DestRC == ARM::GPRRegisterClass && + SrcRC == ARM::tGPRRegisterClass) || + (DestRC == ARM::tGPRRegisterClass && + SrcRC == ARM::GPRRegisterClass)) { + AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), + DestReg).addReg(SrcReg))); + return true; + } + + return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC); +} diff --git a/lib/Target/ARM/Thumb2InstrInfo.h b/lib/Target/ARM/Thumb2InstrInfo.h index d408a7cffaf..ac31707ab78 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.h +++ b/lib/Target/ARM/Thumb2InstrInfo.h @@ -37,6 +37,12 @@ public: // Return true if the block does not fall through. bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; + bool copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). diff --git a/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll new file mode 100644 index 00000000000..c1fceee9f53 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll @@ -0,0 +1,35 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" +target triple = "thumbv6t2-elf" + %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }> + +declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind + +define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind { +entry: + br i1 undef, label %bb1, label %bb13 + +bb1: ; preds = %entry + %tmp38 = add i32 undef, 10 ; [#uses=1] + br label %bb.i + +bb.i: ; preds = %bb.i, %bb1 + %indvar.i = phi i32 [ 0, %bb1 ], [ %2, %bb.i ] ; [#uses=3] + %tmp39 = add i32 %indvar.i, %tmp38 ; [#uses=1] + %p_addr.0.i = getelementptr i8* undef, i32 %tmp39 ; [#uses=1] + %0 = load i8* %p_addr.0.i, align 1 ; [#uses=1] + %1 = icmp slt i8 %0, 0 ; [#uses=1] + %2 = add i32 %indvar.i, 1 ; [#uses=1] + br i1 %1, label %bb.i, label %read_uleb128.exit + +read_uleb128.exit: ; preds = %bb.i + %.sum40 = add i32 %indvar.i, undef ; [#uses=1] + %.sum31 = add i32 %.sum40, 2 ; [#uses=1] + %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31 ; [#uses=1] + %3 = call arm_apcscc i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; [#uses=0] + unreachable + +bb13: ; preds = %entry + ret i32 0 +}