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Fix the rest of the ARM failures by converting them to FileCheck.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85208 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-27 06:16:45 +00:00
parent 13e80bdb71
commit b9350315d2
7 changed files with 74 additions and 39 deletions
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13
test/CodeGen/ARM/fpmem.ll
View File

@ -1,21 +1,22 @@
; RUN: llc < %s -march=arm | \
; RUN: grep {mov r0, #0} | count 1
; RUN: llc < %s -march=arm -mattr=+vfp2 | \
; RUN: grep {flds.*\\\[} | count 1
; RUN: llc < %s -march=arm -mattr=+vfp2 | \
; RUN: grep {fsts.*\\\[} | count 1
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) {
; CHECK: f1:
; CHECK: mov r0, #0
ret float 0.000000e+00
}
define float @f2(float* %v, float %u) {
; CHECK: f2:
; CHECK: flds{{.*}}[
%tmp = load float* %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
ret float %tmp1
}
define void @f3(float %a, float %b, float* %v) {
; CHECK: f3:
; CHECK: fsts{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1]
store float %tmp, float* %v
ret void

3
test/CodeGen/ARM/ispositive.ll
View File

@ -1,6 +1,7 @@
; RUN: llc < %s -march=arm | grep {mov r0, r0, lsr #31}
; RUN: llc < %s -march=arm | FileCheck %s
define i32 @test1(i32 %X) {
; CHECK: mov r0, r0, lsr #31
entry:
icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
zext i1 %0 to i32 ; <i32>:1 [#uses=1]

14
test/CodeGen/ARM/ldm.ll
View File

@ -1,13 +1,10 @@
; RUN: llc < %s -march=arm | \
; RUN: grep ldmia | count 2
; RUN: llc < %s -march=arm | \
; RUN: grep ldmib | count 1
; RUN: llc < %s -mtriple=arm-apple-darwin | \
; RUN: grep {ldmfd sp\!} | count 3
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
define i32 @t1() {
; CHECK: t1:
; CHECK: ldmia
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
%tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
@ -15,6 +12,8 @@ define i32 @t1() {
}
define i32 @t2() {
; CHECK: t2:
; CHECK: ldmia
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
@ -23,6 +22,9 @@ define i32 @t2() {
}
define i32 @t3() {
; CHECK: t3:
; CHECK: ldmib
; CHECK: ldmfd sp!
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]

22
test/CodeGen/ARM/ldr.ll
View File

@ -1,16 +1,16 @@
; RUN: llc < %s -march=arm | grep {ldr r0} | count 7
; RUN: llc < %s -march=arm | grep mov | grep 1
; RUN: llc < %s -march=arm | not grep mvn
; RUN: llc < %s -march=arm | grep ldr | grep lsl
; RUN: llc < %s -march=arm | grep ldr | grep lsr
; RUN: llc < %s -march=arm | FileCheck %s
define i32 @f1(i32* %v) {
; CHECK: f1:
; CHECK: ldr r0
entry:
%tmp = load i32* %v
ret i32 %tmp
}
define i32 @f2(i32* %v) {
; CHECK: f2:
; CHECK: ldr r0
entry:
%tmp2 = getelementptr i32* %v, i32 1023
%tmp = load i32* %tmp2
@ -18,6 +18,9 @@ entry:
}
define i32 @f3(i32* %v) {
; CHECK: f3:
; CHECK: mov
; CHECK: ldr r0
entry:
%tmp2 = getelementptr i32* %v, i32 1024
%tmp = load i32* %tmp2
@ -25,6 +28,9 @@ entry:
}
define i32 @f4(i32 %base) {
; CHECK: f4:
; CHECK-NOT: mvn
; CHECK: ldr r0
entry:
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i32*
@ -33,6 +39,8 @@ entry:
}
define i32 @f5(i32 %base, i32 %offset) {
; CHECK: f5:
; CHECK: ldr r0
entry:
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i32*
@ -41,6 +49,8 @@ entry:
}
define i32 @f6(i32 %base, i32 %offset) {
; CHECK: f6:
; CHECK: ldr r0{{.*}}lsl{{.*}}
entry:
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
@ -50,6 +60,8 @@ entry:
}
define i32 @f7(i32 %base, i32 %offset) {
; CHECK: f7:
; CHECK: ldr r0{{.*}}lsr{{.*}}
entry:
%tmp1 = lshr i32 %offset, 2
%tmp2 = add i32 %base, %tmp1

34
test/CodeGen/ARM/long.ll
View File

@ -1,47 +1,50 @@
; RUN: llc < %s -march=arm -asm-verbose | \
; RUN: grep -- {-2147483648} | count 3
; RUN: llc < %s -march=arm | grep mvn | count 3
; RUN: llc < %s -march=arm | grep adds | count 1
; RUN: llc < %s -march=arm | grep adc | count 1
; RUN: llc < %s -march=arm | grep {subs } | count 1
; RUN: llc < %s -march=arm | grep sbc | count 1
; RUN: llc < %s -march=arm | \
; RUN: grep smull | count 1
; RUN: llc < %s -march=arm | \
; RUN: grep umull | count 1
; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1() {
; CHECK: f1:
entry:
ret i64 0
}
define i64 @f2() {
; CHECK: f2:
entry:
ret i64 1
}
define i64 @f3() {
; CHECK: f3:
; CHECK: mvn{{.*}}-2147483648
entry:
ret i64 2147483647
}
define i64 @f4() {
; CHECK: f4:
; CHECK: -2147483648
entry:
ret i64 2147483648
}
define i64 @f5() {
; CHECK: f5:
; CHECK: mvn
; CHECK: mvn{{.*}}-2147483648
entry:
ret i64 9223372036854775807
}
define i64 @f6(i64 %x, i64 %y) {
; CHECK: f6:
; CHECK: adds
; CHECK: adc
entry:
%tmp1 = add i64 %y, 1 ; <i64> [#uses=1]
ret i64 %tmp1
}
define void @f7() {
; CHECK: f7:
entry:
%tmp = call i64 @f8( ) ; <i64> [#uses=0]
ret void
@ -50,12 +53,17 @@ entry:
declare i64 @f8()
define i64 @f9(i64 %a, i64 %b) {
; CHECK: f9:
; CHECK: subs r
; CHECK: sbc
entry:
%tmp = sub i64 %a, %b ; <i64> [#uses=1]
ret i64 %tmp
}
define i64 @f(i32 %a, i32 %b) {
; CHECK: f:
; CHECK: smull
entry:
%tmp = sext i32 %a to i64 ; <i64> [#uses=1]
%tmp1 = sext i32 %b to i64 ; <i64> [#uses=1]
@ -64,6 +72,8 @@ entry:
}
define i64 @g(i32 %a, i32 %b) {
; CHECK: g:
; CHECK: umull
entry:
%tmp = zext i32 %a to i64 ; <i64> [#uses=1]
%tmp1 = zext i32 %b to i64 ; <i64> [#uses=1]
@ -72,9 +82,9 @@ entry:
}
define i64 @f10() {
; CHECK: f10:
entry:
%a = alloca i64, align 8 ; <i64*> [#uses=1]
%retval = load i64* %a ; <i64> [#uses=1]
ret i64 %retval
}

9
test/CodeGen/ARM/str_post.ll
View File

@ -1,9 +1,8 @@
; RUN: llc < %s -march=arm | \
; RUN: grep {strh .*\\\[.*\], #-4} | count 1
; RUN: llc < %s -march=arm | \
; RUN: grep {str .*\\\[.*\],} | count 1
; RUN: llc < %s -march=arm | FileCheck %s
define i16 @test1(i32* %X, i16* %A) {
; CHECK: test1:
; CHECK: strh {{.*}}[{{.*}}], #-4
%Y = load i32* %X ; <i32> [#uses=1]
%tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1]
store i16 %tmp1, i16* %A
@ -13,6 +12,8 @@ define i16 @test1(i32* %X, i16* %A) {
}
define i32 @test2(i32* %X, i32* %A) {
; CHECK: test2:
; CHECK: str {{.*}}[{{.*}}],
%Y = load i32* %X ; <i32> [#uses=1]
store i32 %Y, i32* %A
%tmp1 = ptrtoint i32* %A to i32 ; <i32> [#uses=1]

18
test/CodeGen/ARM/tls2.ll
View File

@ -1,19 +1,27 @@
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {i(gottpoff)}
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \
; RUN: grep {ldr r., \[pc, r.\]}
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
; RUN: -relocation-model=pic | grep {__tls_get_addr}
; RUN: | FileCheck %s -check-prefix=CHECK-NONPIC
; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECK-PIC
@i = external thread_local global i32 ; <i32*> [#uses=2]
define i32 @f() {
; CHECK-NONPIC: f:
; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}]
; CHECK-NONPIC: i(gottpoff)
; CHECK-PIC: f:
; CHECK-PIC: __tls_get_addr
entry:
%tmp1 = load i32* @i ; <i32> [#uses=1]
ret i32 %tmp1
}
define i32* @g() {
; CHECK-NONPIC: g:
; CHECK-NONPIC: ldr {{r.}}, [pc, +{{r.}}]
; CHECK-NONPIC: i(gottpoff)
; CHECK-PIC: g:
; CHECK-PIC: __tls_get_addr
entry:
ret i32* @i
}