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Thumb2 ADD/SUB can take SP as a destination register.
It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -639,9 +639,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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// in particular for taking the address of a local.
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// in particular for taking the address of a local.
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let isReMaterializable = 1 in {
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let isReMaterializable = 1 in {
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def ri : T2sTwoRegImm<
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def ri : T2sTwoRegImm<
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(outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
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(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
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opc, ".w\t$Rd, $Rn, $imm",
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opc, ".w\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
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[(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
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let Inst{31-27} = 0b11110;
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{25} = 0;
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let Inst{24} = 1;
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let Inst{24} = 1;
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@ -651,9 +651,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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}
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}
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// 12-bit imm
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// 12-bit imm
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def ri12 : T2I<
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def ri12 : T2I<
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(outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
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(outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
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!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
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!strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
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[(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
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[(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
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bits<4> Rd;
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rn;
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bits<12> imm;
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bits<12> imm;
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@ -669,9 +669,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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let Inst{7-0} = imm{7-0};
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let Inst{7-0} = imm{7-0};
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}
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}
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// register
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// register
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def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
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def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
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opc, ".w\t$Rd, $Rn, $Rm",
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IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
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[(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
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[(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
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let isCommutable = Commutable;
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let isCommutable = Commutable;
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let Inst{31-27} = 0b11101;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{26-25} = 0b01;
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@ -683,9 +683,9 @@ multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
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}
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}
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// shifted register
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// shifted register
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def rs : T2sTwoRegShiftedReg<
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def rs : T2sTwoRegShiftedReg<
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(outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
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(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
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IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
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IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
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[(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
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[(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
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let Inst{31-27} = 0b11101;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{26-25} = 0b01;
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let Inst{24} = 1;
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let Inst{24} = 1;
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@ -3848,24 +3848,24 @@ def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
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// Aliases for ADD without the ".w" optional width specifier.
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// Aliases for ADD without the ".w" optional width specifier.
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
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(t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
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(t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
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def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
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def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
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(t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
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(t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
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(t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
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(t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
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def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
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(t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
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(t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
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pred:$p, cc_out:$s)>;
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pred:$p, cc_out:$s)>;
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// Aliases for SUB without the ".w" optional width specifier.
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// Aliases for SUB without the ".w" optional width specifier.
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
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(t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
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(t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
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def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
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def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
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(t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
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(t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
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(t2SUBrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
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(t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
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def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
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(t2SUBrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
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(t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
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pred:$p, cc_out:$s)>;
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pred:$p, cc_out:$s)>;
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// Alias for compares without the ".w" optional width specifier.
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// Alias for compares without the ".w" optional width specifier.
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