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Merging r235662:
------------------------------------------------------------------------ r235662 | thomas.stellard | 2015-04-23 18:59:24 -0400 (Thu, 23 Apr 2015) | 2 lines R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236450 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -826,11 +826,9 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
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SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Args;
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SDValue A = Op.getOperand(0);
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SDValue B = Op.getOperand(1);
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DAG.ExtractVectorElements(A, Args);
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DAG.ExtractVectorElements(B, Args);
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for (const SDUse &U : Op->ops())
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DAG.ExtractVectorElements(U.get(), Args);
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
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}
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@@ -283,3 +283,14 @@ define void @test_concat_v16i16(<32 x i16> addrspace(1)* %out, <16 x i16> %a, <1
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store <32 x i16> %concat, <32 x i16> addrspace(1)* %out, align 64
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ret void
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}
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; FUNC-LABEL: {{^}}concat_vector_crash:
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; SI: s_endpgm
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define void @concat_vector_crash(<8 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
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bb:
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%tmp = load <2 x float> addrspace(1)* %in, align 4
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%tmp1 = shufflevector <2 x float> %tmp, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%tmp2 = shufflevector <8 x float> undef, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
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store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
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ret void
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}
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