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Merging r235662:

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r235662 | thomas.stellard | 2015-04-23 18:59:24 -0400 (Thu, 23 Apr 2015) | 2 lines

R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operands

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236450 91177308-0d34-0410-b5e6-96231b3b80d8
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Tom Stellard committed 2015-05-04 19:50:14 +00:00
1 parent c64ec2996c
commit b968a2dced
2 files changed
+13 -4
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lib/Target/R600/AMDGPUISelLowering.cpp
+2 -4
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@@ -826,11 +826,9 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
SelectionDAG &DAG) const {
SmallVector<SDValue, 8> Args;
SDValue A = Op.getOperand(0);
SDValue B = Op.getOperand(1);
DAG.ExtractVectorElements(A, Args);
DAG.ExtractVectorElements(B, Args);
for (const SDUse &U : Op->ops())
DAG.ExtractVectorElements(U.get(), Args);
return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
}