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[mips] Add more Octeon cnMips instructions

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Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kai Nacke
2014-04-02 18:40:43 +00:00
parent 6408bdcacd
commit b96fc4a5ea
4 changed files with 87 additions and 12 deletions
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37
lib/Target/Mips/Mips64InstrInfo.td
View File

@@ -234,29 +234,45 @@ let Predicates = [HasCnMips] in {
class Count1s<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr>;
[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
NoItinerary, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rt = $rs";
}
class SetCC64_R<string opstr, PatFrag cond_op> :
InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
II_SEQ_SNE, FrmR, opstr>;
II_SEQ_SNE, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
// Unsigned Byte Add
def BADDu : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
"baddu\t$rd, $rs, $rt",
[(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs,
GPR64Opnd:$rt), 255))],
II_BADDU, FrmR, "baddu">, ADD_FM<0x1c, 0x28> {
let isCommutable = 1;
let isReMaterializable = 1;
}
let Pattern = [(set GPR64Opnd:$rd,
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
ADD_FM<0x1c, 0x28>;
// Multiply Doubleword to GPR
let Defs = [HI0, LO0, P0, P1, P2] in
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
ADD_FM<0x1c, 0x03>;
// Extract a signed bit field /+32
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
// Clear and insert a bit field /+32
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
// Move to multiplier/product register
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
@@ -275,6 +291,7 @@ def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
}
}
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//

16
lib/Target/Mips/MipsInstrFormats.td
View File

@@ -489,6 +489,22 @@ class WAIT_FM : StdArch {
let Inst{5-0} = 0x20;
}
class EXTS_FM<bits<6> funct> : StdArch {
bits<5> rt;
bits<5> rs;
bits<5> pos;
bits<5> lenm1;
bits<32> Inst;
let Inst{31-26} = 0x1c;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-11} = lenm1;
let Inst{10-6} = pos;
let Inst{5-0} = funct;
}
class MTMR_FM<bits<6> funct> : StdArch {
bits<5> rs;