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Typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53504 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1055,7 +1055,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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// The live range [12, 14) are not part of the r1024 live interval since
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// it's defined by an implicit def. It will not conflicts with live
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// interval of r1025. Now suppose both registers are spilled, you can
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// easier see a situation where both registers are reloaded before
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// easily see a situation where both registers are reloaded before
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// the INSERT_SUBREG and both target registers that would overlap.
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HasUse = false;
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@ -1248,7 +1248,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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// The live range [12, 14) are not part of the r1024 live interval since
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// it's defined by an implicit def. It will not conflicts with live
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// interval of r1025. Now suppose both registers are spilled, you can
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// easier see a situation where both registers are reloaded before
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// easily see a situation where both registers are reloaded before
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// the INSERT_SUBREG and both target registers that would overlap.
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continue;
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RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));
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