git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53504 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-07-12 02:22:07 +00:00
parent 79a796c2b1
commit b9890ae3c3

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@ -1055,7 +1055,7 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
// The live range [12, 14) are not part of the r1024 live interval since
// it's defined by an implicit def. It will not conflicts with live
// interval of r1025. Now suppose both registers are spilled, you can
// easier see a situation where both registers are reloaded before
// easily see a situation where both registers are reloaded before
// the INSERT_SUBREG and both target registers that would overlap.
HasUse = false;
@ -1248,7 +1248,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
// The live range [12, 14) are not part of the r1024 live interval since
// it's defined by an implicit def. It will not conflicts with live
// interval of r1025. Now suppose both registers are spilled, you can
// easier see a situation where both registers are reloaded before
// easily see a situation where both registers are reloaded before
// the INSERT_SUBREG and both target registers that would overlap.
continue;
RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));