Fix some 80 column violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173006 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-01-21 06:21:54 +00:00
parent b84b423634
commit b99bafe36d

View File

@ -7508,8 +7508,7 @@ X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
SDValue SDValue
X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
int64_t Offset, int64_t Offset, SelectionDAG &DAG) const {
SelectionDAG &DAG) const {
// Create the TargetGlobalAddress node, folding in the constant // Create the TargetGlobalAddress node, folding in the constant
// offset if it is legal. // offset if it is legal.
unsigned char OpFlags = unsigned char OpFlags =
@ -7729,7 +7728,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
case TLSModel::LocalExec: case TLSModel::LocalExec:
return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
Subtarget->is64Bit(), Subtarget->is64Bit(),
getTargetMachine().getRelocationModel() == Reloc::PIC_); getTargetMachine().getRelocationModel() == Reloc::PIC_);
} }
llvm_unreachable("Unknown TLS model."); llvm_unreachable("Unknown TLS model.");
} }
@ -8108,7 +8107,8 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
SVT == MVT::v8i8 || SVT == MVT::v8i16) && SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
"Custom UINT_TO_FP is not supported!"); "Custom UINT_TO_FP is not supported!");
EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements()); EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
SVT.getVectorNumElements());
return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
} }
@ -8201,8 +8201,9 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
} }
std::pair<SDValue,SDValue> X86TargetLowering:: std::pair<SDValue,SDValue>
FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const { X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
bool IsSigned, bool IsReplace) const {
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
EVT DstTy = Op.getValueType(); EVT DstTy = Op.getValueType();
@ -8704,7 +8705,8 @@ static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able. // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
// //
SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const { SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree."); assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
if (!Subtarget->hasSSE41()) if (!Subtarget->hasSSE41())