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Fix some 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173006 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7508,8 +7508,7 @@ X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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SDValue
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X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
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X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
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int64_t Offset,
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int64_t Offset, SelectionDAG &DAG) const {
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SelectionDAG &DAG) const {
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// Create the TargetGlobalAddress node, folding in the constant
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// Create the TargetGlobalAddress node, folding in the constant
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// offset if it is legal.
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// offset if it is legal.
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unsigned char OpFlags =
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unsigned char OpFlags =
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@ -7729,7 +7728,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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case TLSModel::LocalExec:
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case TLSModel::LocalExec:
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return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
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return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
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Subtarget->is64Bit(),
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Subtarget->is64Bit(),
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getTargetMachine().getRelocationModel() == Reloc::PIC_);
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getTargetMachine().getRelocationModel() == Reloc::PIC_);
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}
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}
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llvm_unreachable("Unknown TLS model.");
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llvm_unreachable("Unknown TLS model.");
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}
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}
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@ -8108,7 +8107,8 @@ SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
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SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
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SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
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"Custom UINT_TO_FP is not supported!");
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"Custom UINT_TO_FP is not supported!");
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EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements());
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EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
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SVT.getVectorNumElements());
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return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
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return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
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DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
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DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
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}
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}
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@ -8201,8 +8201,9 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
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return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
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return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
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}
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}
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std::pair<SDValue,SDValue> X86TargetLowering::
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std::pair<SDValue,SDValue>
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FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
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X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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bool IsSigned, bool IsReplace) const {
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DebugLoc DL = Op.getDebugLoc();
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DebugLoc DL = Op.getDebugLoc();
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EVT DstTy = Op.getValueType();
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EVT DstTy = Op.getValueType();
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@ -8704,7 +8705,8 @@ static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
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// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
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// LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
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//
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//
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SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const {
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SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
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assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
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if (!Subtarget->hasSSE41())
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if (!Subtarget->hasSSE41())
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