6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-12 23:37:33 +00:00
Code Issues Projects Releases Wiki Activity

Rename TargetLowering::getNumElements and friends to

Browse Source 
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37687 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2007-06-21 14:42:22 +00:00
parent 53855ca95c
commit b9f1019696
3 changed files with 23 additions and 23 deletions
include/llvm/Target
TargetLowering.h
lib/CodeGen/SelectionDAG
SelectionDAGISel.cppTargetLowering.cpp

8
include/llvm/Target/TargetLowering.h

@ -347,12 +347,12 @@ public:
return VT == MVT::iPTR ? PointerTy : VT;
}
/// getNumElements - Return the number of registers that this ValueType will
/// getNumRegisters - Return the number of registers that this ValueType will
/// eventually require. This is one for any types promoted to live in larger
/// registers, but may be more than one for types (like i64) that are split
/// into pieces.
unsigned getNumElements(MVT::ValueType VT) const {
return NumElementsForVT[VT];
unsigned getNumRegisters(MVT::ValueType VT) const {
return NumRegistersForVT[VT];
}
/// hasTargetDAGCombine - If true, the target has custom DAG combine
@ -1035,7 +1035,7 @@ private:
/// RegClassForVT - This indicates the default register class to use for
/// each ValueType the target supports natively.
TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
/// TransformToType - For any value types we are promoting or expanding, this
/// contains the value type that we are changing to. For Expanded types, this

28
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@ -290,19 +290,19 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
if (PN->use_empty()) continue;
MVT::ValueType VT = TLI.getValueType(PN->getType());
unsigned NumElements;
unsigned NumRegisters;
if (VT != MVT::Vector)
NumElements = TLI.getNumElements(VT);
NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
NumElements =
NumRegisters =
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
VT1, VT2);
}
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
for (unsigned i = 0; i != NumElements; ++i)
for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
}
}
@ -343,7 +343,7 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
// The common case is that we will only create one register for this
// value. If we have that case, create and return the virtual register.
unsigned NV = TLI.getNumElements(VT);
unsigned NV = TLI.getNumRegisters(VT);
if (NV == 1) {
// If we are promoting this value, pick the next largest supported type.
MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
@ -750,7 +750,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) {
// Source must be expanded. This input value is actually coming from the
// register pair InReg and InReg+1.
MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
unsigned NumVals = TLI.getNumElements(VT);
unsigned NumVals = TLI.getNumRegisters(VT);
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
if (NumVals == 1)
N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
@ -3185,7 +3185,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber,
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
NumRegs = TLI.getNumElements(OpInfo.ConstraintVT);
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
@ -3831,7 +3831,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// integers. Figure out what the destination type is and how many small
// integers it turns into.
MVT::ValueType NVT = getTypeToExpandTo(VT);
unsigned NumVals = getNumElements(VT);
unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i) {
RetVals.push_back(NVT);
// if it isn't first piece, alignment must be 1
@ -4088,7 +4088,7 @@ TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
// integers. Figure out what the source elt type is and how many small
// integers it is.
MVT::ValueType NVT = getTypeToExpandTo(VT);
unsigned NumVals = getNumElements(VT);
unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i)
RetTys.push_back(NVT);
} else {
@ -4507,7 +4507,7 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
return DAG.getCopyToReg(getRoot(), Reg, Op);
} else {
DestVT = TLI.getTypeToExpandTo(SrcVT);
unsigned NumVals = TLI.getNumElements(SrcVT);
unsigned NumVals = TLI.getNumRegisters(SrcVT);
if (NumVals == 1)
return DAG.getCopyToReg(getRoot(), Reg,
DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
@ -4695,16 +4695,16 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
MVT::ValueType VT = TLI.getValueType(PN->getType());
unsigned NumElements;
unsigned NumRegisters;
if (VT != MVT::Vector)
NumElements = TLI.getNumElements(VT);
NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
NumElements =
NumRegisters =
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
VT1, VT2);
}
for (unsigned i = 0, e = NumElements; i != e; ++i)
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
}
}

10
lib/CodeGen/SelectionDAG/TargetLowering.cpp

@ -216,7 +216,7 @@ void TargetLowering::computeRegisterProperties() {
// Everything defaults to one.
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
NumElementsForVT[i] = 1;
NumRegistersForVT[i] = 1;
// Find the largest integer register class.
unsigned LargestIntReg = MVT::i128;
@ -227,12 +227,12 @@ void TargetLowering::computeRegisterProperties() {
// many registers to represent as the previous ValueType.
unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
// Inspect all of the ValueType's possible, deciding how to process them.
for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
// If we are expanding this type, expand it!
if (getNumElements((MVT::ValueType)IntReg) != 1)
if (getNumRegisters((MVT::ValueType)IntReg) != 1)
SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
ValueTypeActions);
else if (!isTypeLegal((MVT::ValueType)IntReg))
@ -250,7 +250,7 @@ void TargetLowering::computeRegisterProperties() {
if (isTypeLegal(MVT::f64))
TransformToType[MVT::f64] = MVT::f64;
else {
NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
ValueTypeActions);
}
@ -260,7 +260,7 @@ void TargetLowering::computeRegisterProperties() {
SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
ValueTypeActions);
else {
NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
ValueTypeActions);
}