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Specify S registers as D registers' sub-registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-04-20 21:20:10 +00:00
parent 6120433e9e
commit ba647becb9
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMRegisterInfo.td
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@ -13,10 +13,10 @@
//===----------------------------------------------------------------------===//
// Registers are identified with 4-bit ID numbers.
class ARMReg<bits<4> num, string n, list<Register> aliases = []> : Register<n> {
class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
field bits<4> Num;
let Namespace = "ARM";
let Aliases = aliases;
let SubRegs = subregs;
}
class ARMFReg<bits<5> num, string n> : Register<n> {