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TableGen'ing instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -15,7 +15,8 @@ TARGET = ARM
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BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
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ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
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ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
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ARMGenDAGISel.inc ARMGenSubtarget.inc
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ARMGenDAGISel.inc ARMGenSubtarget.inc \
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ARMGenCodeEmitter.inc
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DIRS = AsmPrinter
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