TableGen'ing instruction encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55533 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-08-29 07:42:03 +00:00
parent 612b79edc9
commit ba705f62b1

View File

@ -15,7 +15,8 @@ TARGET = ARM
BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
ARMGenDAGISel.inc ARMGenSubtarget.inc
ARMGenDAGISel.inc ARMGenSubtarget.inc \
ARMGenCodeEmitter.inc
DIRS = AsmPrinter