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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Reorganize SIInstructions.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206902 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
b84cc10c3c
commit
baf1d45ec2
@ -36,6 +36,50 @@ def WAIT_FLAG : InstFlag<"printWaitFlag">;
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let Predicates = [isSI] in {
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//===----------------------------------------------------------------------===//
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// SMRD Instructions
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//===----------------------------------------------------------------------===//
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let mayLoad = 1 in {
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// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SGPR_32 register class does not include M0
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// and writing to M0 from an SMRD instruction will hang the GPU.
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defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
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defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
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defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
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defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
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0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
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>;
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defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
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0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
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>;
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defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
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0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
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>;
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defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
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0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
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>;
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defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
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0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
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>;
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} // mayLoad = 1
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//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
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//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
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//===----------------------------------------------------------------------===//
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// SOP1 Instructions
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//===----------------------------------------------------------------------===//
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let neverHasSideEffects = 1 in {
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let isMoveImm = 1 in {
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@ -107,6 +151,160 @@ def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>;
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def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>;
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def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>;
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def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>;
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//===----------------------------------------------------------------------===//
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// SOP2 Instructions
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//===----------------------------------------------------------------------===//
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let Defs = [SCC] in { // Carry out goes to SCC
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let isCommutable = 1 in {
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def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
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def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
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[(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
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>;
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} // End isCommutable = 1
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def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
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def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
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[(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
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>;
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let Uses = [SCC] in { // Carry in comes from SCC
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let isCommutable = 1 in {
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def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
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[(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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} // End isCommutable = 1
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def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
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[(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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} // End Uses = [SCC]
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} // End Defs = [SCC]
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def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
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[(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
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>;
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def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
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[(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
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>;
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def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
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[(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
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>;
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def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
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[(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
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>;
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def S_CSELECT_B32 : SOP2 <
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0x0000000a, (outs SReg_32:$dst),
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(ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
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[]
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>;
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def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
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def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
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[(set i32:$dst, (and i32:$src0, i32:$src1))]
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>;
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def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
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[(set i64:$dst, (and i64:$src0, i64:$src1))]
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>;
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def : Pat <
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(i1 (and i1:$src0, i1:$src1)),
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(S_AND_B64 $src0, $src1)
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>;
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def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
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[(set i32:$dst, (or i32:$src0, i32:$src1))]
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>;
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def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
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[(set i64:$dst, (or i64:$src0, i64:$src1))]
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>;
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def : Pat <
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(i1 (or i1:$src0, i1:$src1)),
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(S_OR_B64 $src0, $src1)
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>;
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def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
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[(set i32:$dst, (xor i32:$src0, i32:$src1))]
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>;
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def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
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[(set i1:$dst, (xor i1:$src0, i1:$src1))]
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>;
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def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
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def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
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def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
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def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
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def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
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def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
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def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
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def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
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def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
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def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
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// Use added complexity so these patterns are preferred to the VALU patterns.
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let AddedComplexity = 1 in {
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def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
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[(set i32:$dst, (shl i32:$src0, i32:$src1))]
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>;
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def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
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[(set i64:$dst, (shl i64:$src0, i32:$src1))]
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>;
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def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
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[(set i32:$dst, (srl i32:$src0, i32:$src1))]
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>;
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def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
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[(set i64:$dst, (srl i64:$src0, i32:$src1))]
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>;
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def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
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[(set i32:$dst, (sra i32:$src0, i32:$src1))]
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>;
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def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
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[(set i64:$dst, (sra i64:$src0, i32:$src1))]
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>;
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} // End AddedComplexity = 1
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def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
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def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
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def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
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def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
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def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
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def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
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def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
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//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
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def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
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//===----------------------------------------------------------------------===//
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// SOPC Instructions
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//===----------------------------------------------------------------------===//
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def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
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def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
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def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
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def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
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def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
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def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
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def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
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def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
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def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
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def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
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def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
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def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
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////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
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////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
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////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
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////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
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//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
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//===----------------------------------------------------------------------===//
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// SOPK Instructions
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//===----------------------------------------------------------------------===//
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def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>;
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def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>;
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@ -155,6 +353,106 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
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//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>;
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//def EXP : EXP_ <0x00000000, "EXP", []>;
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//===----------------------------------------------------------------------===//
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// SOPP Instructions
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//===----------------------------------------------------------------------===//
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//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
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let isTerminator = 1 in {
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def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
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[(IL_retflag)]> {
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let SIMM16 = 0;
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let isBarrier = 1;
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let hasCtrlDep = 1;
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}
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let isBranch = 1 in {
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def S_BRANCH : SOPP <
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0x00000002, (ins brtarget:$target), "S_BRANCH $target",
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[(br bb:$target)]> {
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let isBarrier = 1;
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}
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let DisableEncoding = "$scc" in {
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def S_CBRANCH_SCC0 : SOPP <
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0x00000004, (ins brtarget:$target, SCCReg:$scc),
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"S_CBRANCH_SCC0 $target", []
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>;
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def S_CBRANCH_SCC1 : SOPP <
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0x00000005, (ins brtarget:$target, SCCReg:$scc),
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"S_CBRANCH_SCC1 $target",
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[]
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>;
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} // End DisableEncoding = "$scc"
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def S_CBRANCH_VCCZ : SOPP <
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0x00000006, (ins brtarget:$target, VCCReg:$vcc),
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"S_CBRANCH_VCCZ $target",
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[]
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>;
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def S_CBRANCH_VCCNZ : SOPP <
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0x00000007, (ins brtarget:$target, VCCReg:$vcc),
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"S_CBRANCH_VCCNZ $target",
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[]
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>;
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let DisableEncoding = "$exec" in {
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def S_CBRANCH_EXECZ : SOPP <
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0x00000008, (ins brtarget:$target, EXECReg:$exec),
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"S_CBRANCH_EXECZ $target",
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[]
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>;
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def S_CBRANCH_EXECNZ : SOPP <
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0x00000009, (ins brtarget:$target, EXECReg:$exec),
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"S_CBRANCH_EXECNZ $target",
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[]
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>;
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} // End DisableEncoding = "$exec"
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} // End isBranch = 1
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} // End isTerminator = 1
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let hasSideEffects = 1 in {
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def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
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[(int_AMDGPU_barrier_local)]
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> {
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let SIMM16 = 0;
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let isBarrier = 1;
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let hasCtrlDep = 1;
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let mayLoad = 1;
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let mayStore = 1;
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}
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def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
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[]
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>;
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//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
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//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
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//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
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let Uses = [EXEC] in {
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def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
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[(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
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> {
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let DisableEncoding = "$m0";
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}
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} // End Uses = [EXEC]
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//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
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//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
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//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
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//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
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//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
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//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
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} // End hasSideEffects
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//===----------------------------------------------------------------------===//
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// VOPC Instructions
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//===----------------------------------------------------------------------===//
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let isCompare = 1 in {
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defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">;
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@ -411,6 +709,10 @@ defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
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} // End isCompare = 1
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//===----------------------------------------------------------------------===//
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// DS Instructions
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//===----------------------------------------------------------------------===//
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def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>;
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def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>;
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def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
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@ -435,6 +737,9 @@ def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "DS_READ2_B64", VReg_128>;
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// TODO: DS_READ2ST64_B32, DS_READ2ST64_B64,
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// DS_WRITE2ST64_B32, DS_WRITE2ST64_B64
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//===----------------------------------------------------------------------===//
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// MUBUF Instructions
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//===----------------------------------------------------------------------===//
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//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
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//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>;
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@ -507,6 +812,11 @@ def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
|
||||
//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>;
|
||||
//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>;
|
||||
//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MTBUF Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>;
|
||||
//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>;
|
||||
//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>;
|
||||
@ -516,41 +826,10 @@ def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FOR
|
||||
def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>;
|
||||
def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>;
|
||||
|
||||
let mayLoad = 1 in {
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MIMG Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
|
||||
// SMRD instructions, because the SGPR_32 register class does not include M0
|
||||
// and writing to M0 from an SMRD instruction will hang the GPU.
|
||||
defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>;
|
||||
defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>;
|
||||
defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>;
|
||||
defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>;
|
||||
defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
|
||||
0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
|
||||
0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
|
||||
0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
|
||||
0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
|
||||
0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512
|
||||
>;
|
||||
|
||||
} // mayLoad = 1
|
||||
|
||||
//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
|
||||
//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
|
||||
defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">;
|
||||
defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">;
|
||||
//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>;
|
||||
@ -646,8 +925,12 @@ defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">;
|
||||
//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>;
|
||||
//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>;
|
||||
//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>;
|
||||
//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VOP1 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
|
||||
|
||||
let neverHasSideEffects = 1, isMoveImm = 1 in {
|
||||
defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>;
|
||||
@ -764,6 +1047,11 @@ defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>;
|
||||
defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>;
|
||||
defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VINTRP Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def V_INTERP_P1_F32 : VINTRP <
|
||||
0x00000000,
|
||||
(outs VReg_32:$dst),
|
||||
@ -794,97 +1082,9 @@ def V_INTERP_MOV_F32 : VINTRP <
|
||||
let DisableEncoding = "$m0";
|
||||
}
|
||||
|
||||
//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
|
||||
|
||||
let isTerminator = 1 in {
|
||||
|
||||
def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM",
|
||||
[(IL_retflag)]> {
|
||||
let SIMM16 = 0;
|
||||
let isBarrier = 1;
|
||||
let hasCtrlDep = 1;
|
||||
}
|
||||
|
||||
let isBranch = 1 in {
|
||||
def S_BRANCH : SOPP <
|
||||
0x00000002, (ins brtarget:$target), "S_BRANCH $target",
|
||||
[(br bb:$target)]> {
|
||||
let isBarrier = 1;
|
||||
}
|
||||
|
||||
let DisableEncoding = "$scc" in {
|
||||
def S_CBRANCH_SCC0 : SOPP <
|
||||
0x00000004, (ins brtarget:$target, SCCReg:$scc),
|
||||
"S_CBRANCH_SCC0 $target", []
|
||||
>;
|
||||
def S_CBRANCH_SCC1 : SOPP <
|
||||
0x00000005, (ins brtarget:$target, SCCReg:$scc),
|
||||
"S_CBRANCH_SCC1 $target",
|
||||
[]
|
||||
>;
|
||||
} // End DisableEncoding = "$scc"
|
||||
|
||||
def S_CBRANCH_VCCZ : SOPP <
|
||||
0x00000006, (ins brtarget:$target, VCCReg:$vcc),
|
||||
"S_CBRANCH_VCCZ $target",
|
||||
[]
|
||||
>;
|
||||
def S_CBRANCH_VCCNZ : SOPP <
|
||||
0x00000007, (ins brtarget:$target, VCCReg:$vcc),
|
||||
"S_CBRANCH_VCCNZ $target",
|
||||
[]
|
||||
>;
|
||||
|
||||
let DisableEncoding = "$exec" in {
|
||||
def S_CBRANCH_EXECZ : SOPP <
|
||||
0x00000008, (ins brtarget:$target, EXECReg:$exec),
|
||||
"S_CBRANCH_EXECZ $target",
|
||||
[]
|
||||
>;
|
||||
def S_CBRANCH_EXECNZ : SOPP <
|
||||
0x00000009, (ins brtarget:$target, EXECReg:$exec),
|
||||
"S_CBRANCH_EXECNZ $target",
|
||||
[]
|
||||
>;
|
||||
} // End DisableEncoding = "$exec"
|
||||
|
||||
|
||||
} // End isBranch = 1
|
||||
} // End isTerminator = 1
|
||||
|
||||
let hasSideEffects = 1 in {
|
||||
def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
|
||||
[(int_AMDGPU_barrier_local)]
|
||||
> {
|
||||
let SIMM16 = 0;
|
||||
let isBarrier = 1;
|
||||
let hasCtrlDep = 1;
|
||||
let mayLoad = 1;
|
||||
let mayStore = 1;
|
||||
}
|
||||
|
||||
def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16",
|
||||
[]
|
||||
>;
|
||||
//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>;
|
||||
//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>;
|
||||
//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>;
|
||||
|
||||
let Uses = [EXEC] in {
|
||||
def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16",
|
||||
[(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
|
||||
> {
|
||||
let DisableEncoding = "$m0";
|
||||
}
|
||||
} // End Uses = [EXEC]
|
||||
|
||||
//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>;
|
||||
//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>;
|
||||
//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>;
|
||||
//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>;
|
||||
//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
|
||||
//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
|
||||
} // End hasSideEffects
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VOP2 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
|
||||
(ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
|
||||
@ -1031,23 +1231,10 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
|
||||
>;
|
||||
////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>;
|
||||
////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>;
|
||||
def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32">;
|
||||
def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32">;
|
||||
def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32">;
|
||||
def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32">;
|
||||
def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32">;
|
||||
def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32">;
|
||||
def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32">;
|
||||
def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32">;
|
||||
def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32">;
|
||||
def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32">;
|
||||
def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32">;
|
||||
def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32">;
|
||||
////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>;
|
||||
////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>;
|
||||
////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>;
|
||||
////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>;
|
||||
//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VOP3 Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
|
||||
@ -1169,128 +1356,9 @@ def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
|
||||
//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>;
|
||||
def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>;
|
||||
|
||||
let Defs = [SCC] in { // Carry out goes to SCC
|
||||
let isCommutable = 1 in {
|
||||
def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>;
|
||||
def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32",
|
||||
[(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
|
||||
>;
|
||||
} // End isCommutable = 1
|
||||
|
||||
def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>;
|
||||
def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32",
|
||||
[(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
|
||||
>;
|
||||
|
||||
let Uses = [SCC] in { // Carry in comes from SCC
|
||||
let isCommutable = 1 in {
|
||||
def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32",
|
||||
[(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
|
||||
} // End isCommutable = 1
|
||||
|
||||
def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32",
|
||||
[(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
|
||||
} // End Uses = [SCC]
|
||||
} // End Defs = [SCC]
|
||||
|
||||
def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32",
|
||||
[(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32",
|
||||
[(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32",
|
||||
[(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32",
|
||||
[(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
def S_CSELECT_B32 : SOP2 <
|
||||
0x0000000a, (outs SReg_32:$dst),
|
||||
(ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
|
||||
[]
|
||||
>;
|
||||
|
||||
def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>;
|
||||
|
||||
def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32",
|
||||
[(set i32:$dst, (and i32:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64",
|
||||
[(set i64:$dst, (and i64:$src0, i64:$src1))]
|
||||
>;
|
||||
|
||||
def : Pat <
|
||||
(i1 (and i1:$src0, i1:$src1)),
|
||||
(S_AND_B64 $src0, $src1)
|
||||
>;
|
||||
|
||||
def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32",
|
||||
[(set i32:$dst, (or i32:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64",
|
||||
[(set i64:$dst, (or i64:$src0, i64:$src1))]
|
||||
>;
|
||||
|
||||
def : Pat <
|
||||
(i1 (or i1:$src0, i1:$src1)),
|
||||
(S_OR_B64 $src0, $src1)
|
||||
>;
|
||||
|
||||
def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32",
|
||||
[(set i32:$dst, (xor i32:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64",
|
||||
[(set i1:$dst, (xor i1:$src0, i1:$src1))]
|
||||
>;
|
||||
def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>;
|
||||
def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>;
|
||||
def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>;
|
||||
def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>;
|
||||
def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>;
|
||||
def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>;
|
||||
def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>;
|
||||
def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>;
|
||||
def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>;
|
||||
def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>;
|
||||
|
||||
// Use added complexity so these patterns are preferred to the VALU patterns.
|
||||
let AddedComplexity = 1 in {
|
||||
|
||||
def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32",
|
||||
[(set i32:$dst, (shl i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64",
|
||||
[(set i64:$dst, (shl i64:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32",
|
||||
[(set i32:$dst, (srl i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64",
|
||||
[(set i64:$dst, (srl i64:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32",
|
||||
[(set i32:$dst, (sra i32:$src0, i32:$src1))]
|
||||
>;
|
||||
def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64",
|
||||
[(set i64:$dst, (sra i64:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
} // End AddedComplexity = 1
|
||||
|
||||
def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>;
|
||||
def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>;
|
||||
def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>;
|
||||
def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>;
|
||||
def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>;
|
||||
def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>;
|
||||
def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
|
||||
//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
|
||||
def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pseudo Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let isCodeGenOnly = 1, isPseudo = 1 in {
|
||||
|
||||
@ -1478,6 +1546,53 @@ def : Pat <
|
||||
(V_SUB_F64 $src0, $src1)
|
||||
>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SMRD Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
|
||||
|
||||
// 1. Offset as 8bit DWORD immediate
|
||||
def : Pat <
|
||||
(constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
|
||||
(vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
|
||||
>;
|
||||
|
||||
// 2. Offset loaded in an 32bit SGPR
|
||||
def : Pat <
|
||||
(constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
|
||||
(vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
|
||||
>;
|
||||
|
||||
// 3. No offset at all
|
||||
def : Pat <
|
||||
(constant_load i64:$sbase),
|
||||
(vt (Instr_IMM $sbase, 0))
|
||||
>;
|
||||
}
|
||||
|
||||
defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
|
||||
|
||||
// 1. Offset as 8bit DWORD immediate
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
|
||||
>;
|
||||
|
||||
// 2. Offset loaded in an 32bit SGPR
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, imm:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
|
||||
>;
|
||||
|
||||
|
||||
/********** ======================= **********/
|
||||
/********** Image sampling patterns **********/
|
||||
/********** ======================= **********/
|
||||
@ -1866,19 +1981,7 @@ class Ext32Pat <SDNode ext> : Pat <
|
||||
def : Ext32Pat <zext>;
|
||||
def : Ext32Pat <anyext>;
|
||||
|
||||
// 1. Offset as 8bit DWORD immediate
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
|
||||
>;
|
||||
|
||||
// 2. Offset loaded in an 32bit SGPR
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, imm:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
|
||||
>;
|
||||
|
||||
// 3. Offset in an 32Bit VGPR
|
||||
// Offset in an 32Bit VGPR
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, i32:$voff),
|
||||
(BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0)
|
||||
@ -1953,40 +2056,6 @@ def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
|
||||
def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val),
|
||||
(DS_SUB_U32_RTN 0, $ptr, $val, 0)>;
|
||||
|
||||
/********** ================== **********/
|
||||
/********** SMRD Patterns **********/
|
||||
/********** ================== **********/
|
||||
|
||||
multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
|
||||
|
||||
// 1. Offset as 8bit DWORD immediate
|
||||
def : Pat <
|
||||
(constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
|
||||
(vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
|
||||
>;
|
||||
|
||||
// 2. Offset loaded in an 32bit SGPR
|
||||
def : Pat <
|
||||
(constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)),
|
||||
(vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset)))
|
||||
>;
|
||||
|
||||
// 3. No offset at all
|
||||
def : Pat <
|
||||
(constant_load i64:$sbase),
|
||||
(vt (Instr_IMM $sbase, 0))
|
||||
>;
|
||||
}
|
||||
|
||||
defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
|
||||
defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MUBUF Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user