mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-24 08:24:33 +00:00
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -89,7 +89,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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default:
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llvm_unreachable("<unknown operand type>");
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}
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const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Symbol, Kind, Ctx);
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if (!Offset)
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@ -97,7 +97,7 @@ MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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// Assume offset is never negative.
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assert(Offset > 0);
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const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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const MCBinaryExpr *AddExpr = MCBinaryExpr::CreateAdd(MCSym, OffsetExpr, Ctx);
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return MCOperand::CreateExpr(AddExpr);
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@ -148,7 +148,7 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
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MCInst Sw;
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if (Offset >= 0x8000) {
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unsigned Hi = (Offset >> 16) + ((Offset & 0x8000) != 0);
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unsigned Hi = (Offset >> 16) + ((Offset & 0x8000) != 0);
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Offset &= 0xffff;
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Reg = Mips::AT;
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@ -163,7 +163,7 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
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MCInsts[1].addOperand(MCOperand::CreateReg(Mips::AT));
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MCInsts[1].addOperand(MCOperand::CreateReg(Mips::SP));
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}
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Sw.setOpcode(Mips::SW);
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Sw.addOperand(MCOperand::CreateReg(Mips::GP));
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Sw.addOperand(MCOperand::CreateReg(Reg));
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@ -172,9 +172,9 @@ void MipsMCInstLower::LowerCPRESTORE(const MachineInstr *MI,
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}
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MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
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unsigned offset) const {
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unsigned offset) const {
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MachineOperandType MOTy = MO.getType();
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switch (MOTy) {
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default: llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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@ -199,7 +199,7 @@ MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO,
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void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCOp = LowerOperand(MO);
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@ -210,8 +210,8 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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}
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void MipsMCInstLower::LowerUnalignedLoadStore(const MachineInstr *MI,
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SmallVector<MCInst,
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4>& MCInsts) {
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SmallVector<MCInst,
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4>& MCInsts) {
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unsigned Opc = MI->getOpcode();
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MCInst Instr1, Instr2, Instr3, Move;
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