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Add getAllocatableSet() function.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16059 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos
2004-08-26 22:21:04 +00:00
parent 3921c74652
commit bb4bdf4fe4
2 changed files with 22 additions and 4 deletions
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4
include/llvm/Target/MRegisterInfo.h
View File

@@ -160,6 +160,10 @@ public:
return Reg >= FirstVirtualRegister; return Reg >= FirstVirtualRegister;
} }
/// getAllocatableSet - Returns a bitset indexed by register number
/// indicating if a register is allocatable or not.
std::vector<bool> getAllocatableSet(MachineFunction &MF) const;
const MRegisterDesc &operator[](unsigned RegNo) const { const MRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs && assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!"); "Attempting to access record for invalid register number!");

22
lib/Target/MRegisterInfo.cpp
View File

@@ -28,12 +28,14 @@ MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR,
// Fill in the PhysRegClasses map // Fill in the PhysRegClasses map
for (MRegisterInfo::regclass_iterator I = regclass_begin(), for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I) E = regclass_end(); I != E; ++I) {
for (unsigned i = 0, e = (*I)->getNumRegs(); i != e; ++i) { const TargetRegisterClass *RC = *I;
unsigned Reg = (*I)->getRegister(i); for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) {
unsigned Reg = RC->getRegister(i);
assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?"); assert(PhysRegClasses[Reg] == 0 && "Register in more than one class?");
PhysRegClasses[Reg] = *I; PhysRegClasses[Reg] = RC;
} }
}
CallFrameSetupOpcode = CFSO; CallFrameSetupOpcode = CFSO;
CallFrameDestroyOpcode = CFDO; CallFrameDestroyOpcode = CFDO;
@@ -44,4 +46,16 @@ MRegisterInfo::~MRegisterInfo() {
delete[] PhysRegClasses; delete[] PhysRegClasses;
} }
std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
std::vector<bool> Allocatable(NumRegs);
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I) {
const TargetRegisterClass *RC = *I;
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
Allocatable[*I] = true;
}
return Allocatable;
}
} // End llvm namespace } // End llvm namespace