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Fix an assertion failure caused by v1i64 in DAGCombiner Shrink.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209798 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hao Liu
2014-05-29 09:19:07 +00:00
parent 2a747bf1c5
commit bb7f18abf8
3 changed files with 27 additions and 16 deletions
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4
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@@ -327,6 +327,10 @@ TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
assert(Op.getNode()->getNumValues() == 1 &&
"ShrinkDemandedOp only supports nodes with one result!");
// Early return, as this function cannot handle vector types.
if (Op.getValueType().isVector())
return false;
// Don't do this if the node has another user, which may require the
// full value.
if (!Op.getNode()->hasOneUse())

25
lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -6047,18 +6047,14 @@ bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
return false;
unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
if (NumBits1 <= NumBits2)
return false;
return true;
return NumBits1 > NumBits2;
}
bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
if (!VT1.isInteger() || !VT2.isInteger())
if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
return false;
unsigned NumBits1 = VT1.getSizeInBits();
unsigned NumBits2 = VT2.getSizeInBits();
if (NumBits1 <= NumBits2)
return false;
return true;
return NumBits1 > NumBits2;
}
// All 32-bit GPR operations implicitly zero the high-half of the corresponding
@@ -6068,18 +6064,14 @@ bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
return false;
unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
if (NumBits1 == 32 && NumBits2 == 64)
return true;
return false;
return NumBits1 == 32 && NumBits2 == 64;
}
bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
if (!VT1.isInteger() || !VT2.isInteger())
if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
return false;
unsigned NumBits1 = VT1.getSizeInBits();
unsigned NumBits2 = VT2.getSizeInBits();
if (NumBits1 == 32 && NumBits2 == 64)
return true;
return false;
return NumBits1 == 32 && NumBits2 == 64;
}
bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
@@ -6092,8 +6084,9 @@ bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
return false;
// 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
return (VT1.isSimple() && VT1.isInteger() && VT2.isSimple() &&
VT2.isInteger() && VT1.getSizeInBits() <= 32);
return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
VT1.getSizeInBits() <= 32);
}
bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,

14
test/CodeGen/AArch64/2014-05-16-shrink-v1i64.ll Normal file
View File

@@ -0,0 +1,14 @@
; RUN: llc -march=arm64 < %s
; The DAGCombiner tries to do following shrink:
; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
; But currently it can't handle vector type and will trigger an assertion failure
; when it tries to generate an add mixed using vector type and scaler type.
; This test checks that such assertion failur should not happen.
define <1 x i64> @dotest(<1 x i64> %in0) {
entry:
%0 = add <1 x i64> %in0, %in0
%vshl_n = shl <1 x i64> %0, <i64 32>
%vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
ret <1 x i64> %vsra_n
}