From bba9aa3475e307be7bd60eecc733cd46eeaf107a Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 10 Oct 2005 16:51:40 +0000 Subject: [PATCH] Add ISD::ADD to MaskedValueIsZero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23685 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 60bb6c6795d..f15ce5784c6 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -215,6 +215,14 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); } return false; + case ISD::ADD: + // (add X, Y) & C == 0 iff (X&C)&(Y&C) == 0 and all bits are low bits. + if ((Mask&(Mask+1)) == 0) { // All low bits + if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && + MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) + return true; + } + break; case ISD::SUB: if (ConstantSDNode *CLHS = dyn_cast(Op.getOperand(0))) { // We know that the top bits of C-X are clear if X contains less bits