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Add ISD::ADD to MaskedValueIsZero

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23685 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-10 16:51:40 +00:00
parent 3892560680
commit bba9aa3475
1 changed files with 8 additions and 0 deletions
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8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -215,6 +215,14 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
} }
return false; return false;
case ISD::ADD:
// (add X, Y) & C == 0 iff (X&C)&(Y&C) == 0 and all bits are low bits.
if ((Mask&(Mask+1)) == 0) { // All low bits
if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
return true;
}
break;
case ISD::SUB: case ISD::SUB:
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
// We know that the top bits of C-X are clear if X contains less bits // We know that the top bits of C-X are clear if X contains less bits