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R600: Use new fmad node.
This enables a few useful combines that used to only use fma. Also since v_mad_f32 apparently does not support denormals, disable the existing cases that are custom handled if they are requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230071 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault committed
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8 files changed
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@@ -133,6 +133,10 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setOperationAction(ISD::FREM, MVT::f32, Custom);
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setOperationAction(ISD::FREM, MVT::f64, Custom);
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// v_mad_f32 does not support denormals according to some sources.
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if (!Subtarget->hasFP32Denormals())
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setOperationAction(ISD::FMAD, MVT::f32, Legal);
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// Lower floating point store/load to integer store/load to reduce the number
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// of patterns in tablegen.
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setOperationAction(ISD::STORE, MVT::f32, Promote);
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@@ -384,6 +388,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setBooleanContents(ZeroOrNegativeOneBooleanContent);
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setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
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@@ -2611,7 +2618,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(DWORDADDR)
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NODE_NAME_CASE(FRACT)
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NODE_NAME_CASE(CLAMP)
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NODE_NAME_CASE(MAD)
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NODE_NAME_CASE(FMAX_LEGACY)
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NODE_NAME_CASE(SMAX)
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NODE_NAME_CASE(UMAX)
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@@ -218,7 +218,6 @@ enum {
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DWORDADDR,
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FRACT,
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CLAMP,
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MAD, // Multiply + add with same result as the separate operations.
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// SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
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// Denormals handled on some parts.
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@@ -78,7 +78,6 @@ def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
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>;
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def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
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def AMDGPUmad : SDNode<"AMDGPUISD::MAD", SDTFPTernaryOp, []>;
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// out = max(a, b) a and b are signed ints
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def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
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@@ -413,11 +413,6 @@ def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
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// Misc Pattern Fragments
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//===----------------------------------------------------------------------===//
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def fmad : PatFrag <
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(ops node:$src0, node:$src1, node:$src2),
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(fadd (fmul node:$src0, node:$src1), node:$src2)
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>;
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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@@ -920,7 +920,7 @@ class MULADD_Common <bits<5> inst> : R600_3OP <
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class MULADD_IEEE_Common <bits<5> inst> : R600_3OP <
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inst, "MULADD_IEEE",
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[(set f32:$dst, (fadd (fmul f32:$src0, f32:$src1), f32:$src2))]
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[(set f32:$dst, (fmad f32:$src0, f32:$src1, f32:$src2))]
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>;
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class FMA_Common <bits<5> inst> : R600_3OP <
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@@ -680,8 +680,9 @@ bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
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case MVT::f32:
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// This is as fast on some subtargets. However, we always have full rate f32
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// mad available which returns the same result as the separate operations
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// which we should prefer over fma.
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return false;
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// which we should prefer over fma. We can't use this if we want to support
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// denormals, so only report this in these cases.
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return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
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case MVT::f64:
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return true;
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default:
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@@ -1642,6 +1643,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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if (VT != MVT::f32)
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break;
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// Only do this if we are not trying to support denormals. v_mad_f32 does
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// not support denormals ever.
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if (Subtarget->hasFP32Denormals())
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break;
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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@@ -1653,7 +1659,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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SDValue A = LHS.getOperand(0);
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if (A == LHS.getOperand(1)) {
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const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, RHS);
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return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
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}
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}
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@@ -1662,11 +1668,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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SDValue A = RHS.getOperand(0);
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if (A == RHS.getOperand(1)) {
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const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, LHS);
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return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
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}
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}
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break;
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return SDValue();
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}
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case ISD::FSUB: {
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if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
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@@ -1676,30 +1682,13 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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// Try to get the fneg to fold into the source modifier. This undoes generic
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// DAG combines and folds them into the mad.
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if (VT == MVT::f32) {
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//
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// Only do this if we are not trying to support denormals. v_mad_f32 does
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// not support denormals ever.
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if (VT == MVT::f32 &&
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!Subtarget->hasFP32Denormals()) {
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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if (LHS.getOpcode() == ISD::FMUL) {
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// (fsub (fmul a, b), c) -> mad a, b, (fneg c)
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SDValue A = LHS.getOperand(0);
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SDValue B = LHS.getOperand(1);
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SDValue C = DAG.getNode(ISD::FNEG, DL, VT, RHS);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
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}
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if (RHS.getOpcode() == ISD::FMUL) {
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// (fsub c, (fmul a, b)) -> mad (fneg a), b, c
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SDValue A = DAG.getNode(ISD::FNEG, DL, VT, RHS.getOperand(0));
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SDValue B = RHS.getOperand(1);
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SDValue C = LHS;
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
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}
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if (LHS.getOpcode() == ISD::FADD) {
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// (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
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@@ -1708,7 +1697,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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const SDValue Two = DAG.getConstantFP(2.0, MVT::f32);
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SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, NegRHS);
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return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
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}
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}
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@@ -1718,9 +1707,11 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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SDValue A = RHS.getOperand(0);
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if (A == RHS.getOperand(1)) {
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const SDValue NegTwo = DAG.getConstantFP(-2.0, MVT::f32);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, NegTwo, A, LHS);
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return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
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}
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}
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return SDValue();
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}
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break;
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@@ -2783,9 +2783,6 @@ def : Pat <
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(V_MUL_HI_I32 $src0, $src1)
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>;
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def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
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defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
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def : ROTRPattern <V_ALIGNBIT_B32>;
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@@ -0,0 +1,567 @@
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; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma.
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-prefix=FUNC %s
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; Make sure we don't form mad with denormals
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; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM-SLOWFMAF -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() #0
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declare float @llvm.fabs.f32(float) #0
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declare float @llvm.fma.f32(float, float, float) #0
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declare float @llvm.fmuladd.f32(float, float, float) #0
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; (fadd (fmul x, y), z) -> (fma x, y, z)
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; FUNC-LABEL: {{^}}combine_to_mad_f32_0:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-DENORM-SLOWFMAF-NOT: v_fma
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; SI-DENORM-SLOWFMAF-NOT: v_mad
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; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
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; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
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; SI: buffer_store_dword [[RESULT]]
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define void @combine_to_mad_f32_0(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
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%tid = tail call i32 @llvm.r600.read.tidig.x() #0
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0
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%b = load float addrspace(1)* %gep.1
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%c = load float addrspace(1)* %gep.2
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%mul = fmul float %a, %b
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%fma = fadd float %mul, %c
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store float %fma, float addrspace(1)* %gep.out
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ret void
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}
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; (fadd (fmul x, y), z) -> (fma x, y, z)
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; FUNC-LABEL: {{^}}combine_to_mad_f32_0_2use:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
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; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
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; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
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; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
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; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT0:v[0-9]+]], [[C]], [[TMP]]
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; SI-DENORM-SLOWFMAF-DAG: v_add_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
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; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI: s_endpgm
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define void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
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%tid = tail call i32 @llvm.r600.read.tidig.x() #0
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
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%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
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%gep.out.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.out.1 = getelementptr float addrspace(1)* %gep.out.0, i32 1
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%a = load float addrspace(1)* %gep.0
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%b = load float addrspace(1)* %gep.1
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%c = load float addrspace(1)* %gep.2
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%d = load float addrspace(1)* %gep.3
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%mul = fmul float %a, %b
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%fma0 = fadd float %mul, %c
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%fma1 = fadd float %mul, %d
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store float %fma0, float addrspace(1)* %gep.out.0
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store float %fma1, float addrspace(1)* %gep.out.1
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ret void
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}
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; (fadd x, (fmul y, z)) -> (fma y, z, x)
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; FUNC-LABEL: {{^}}combine_to_mad_f32_1:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
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; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
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; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
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; SI: buffer_store_dword [[RESULT]]
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define void @combine_to_mad_f32_1(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
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%tid = tail call i32 @llvm.r600.read.tidig.x() #0
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.0
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%b = load float addrspace(1)* %gep.1
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%c = load float addrspace(1)* %gep.2
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%mul = fmul float %a, %b
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%fma = fadd float %c, %mul
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store float %fma, float addrspace(1)* %gep.out
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ret void
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}
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; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
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; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32:
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
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; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
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; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
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||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%fma = fsub float %mul, %c
|
||||
store float %fma, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32_2use:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
|
||||
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT0:v[0-9]+]], [[C]], [[TMP]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
|
||||
|
||||
; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.out.0 = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
%gep.out.1 = getelementptr float addrspace(1)* %gep.out.0, i32 1
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
%d = load float addrspace(1)* %gep.3
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%fma0 = fsub float %mul, %c
|
||||
%fma1 = fsub float %mul, %d
|
||||
store float %fma0, float addrspace(1)* %gep.out.0
|
||||
store float %fma1, float addrspace(1)* %gep.out.1
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
|
||||
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%fma = fsub float %c, %mul
|
||||
store float %fma, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32_2use:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
|
||||
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT0:v[0-9]+]], [[TMP]], [[C]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[TMP]], [[D]]
|
||||
|
||||
; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.out.0 = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
%gep.out.1 = getelementptr float addrspace(1)* %gep.out.0, i32 1
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
%d = load float addrspace(1)* %gep.3
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%fma0 = fsub float %c, %mul
|
||||
%fma1 = fsub float %d, %mul
|
||||
store float %fma0, float addrspace(1)* %gep.out.0
|
||||
store float %fma1, float addrspace(1)* %gep.out.1
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
|
||||
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[TMP]], [[C]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]]
|
||||
define void @combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%mul.neg = fsub float -0.0, %mul
|
||||
%fma = fsub float %mul.neg, %c
|
||||
|
||||
store float %fma, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_neg:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT0:v[0-9]+]], -[[TMP]], [[C]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT1:v[0-9]+]], -[[TMP]], [[D]]
|
||||
|
||||
; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.out.0 = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
%gep.out.1 = getelementptr float addrspace(1)* %gep.out.0, i32 1
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
%d = load float addrspace(1)* %gep.3
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%mul.neg = fsub float -0.0, %mul
|
||||
%fma0 = fsub float %mul.neg, %c
|
||||
%fma1 = fsub float %mul.neg, %d
|
||||
|
||||
store float %fma0, float addrspace(1)* %gep.out.0
|
||||
store float %fma1, float addrspace(1)* %gep.out.1
|
||||
ret void
|
||||
}
|
||||
|
||||
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
|
||||
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_mul:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
|
||||
; SI-DENORM-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_sub_f32_e64 [[RESULT0:v[0-9]+]], -[[TMP]], [[C]]
|
||||
; SI-DENORM-SLOWFMAF-DAG: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[D]], [[TMP]]
|
||||
|
||||
; SI-DAG: buffer_store_dword [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.out.0 = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
%gep.out.1 = getelementptr float addrspace(1)* %gep.out.0, i32 1
|
||||
|
||||
%a = load float addrspace(1)* %gep.0
|
||||
%b = load float addrspace(1)* %gep.1
|
||||
%c = load float addrspace(1)* %gep.2
|
||||
%d = load float addrspace(1)* %gep.3
|
||||
|
||||
%mul = fmul float %a, %b
|
||||
%mul.neg = fsub float -0.0, %mul
|
||||
%fma0 = fsub float %mul.neg, %c
|
||||
%fma1 = fsub float %mul, %d
|
||||
|
||||
store float %fma0, float addrspace(1)* %gep.out.0
|
||||
store float %fma1, float addrspace(1)* %gep.out.1
|
||||
ret void
|
||||
}
|
||||
|
||||
; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
|
||||
|
||||
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_0_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
|
||||
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
||||
|
||||
; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
|
||||
; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP1]]
|
||||
|
||||
; SI-DENORM: v_fma_f32 [[TMP0:v[0-9]+]], [[D]], [[E]], -[[C]]
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP0]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT1:v[0-9]+]], [[C]], [[TMP1]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
define void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.4 = getelementptr float addrspace(1)* %gep.0, i32 4
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%x = load float addrspace(1)* %gep.0
|
||||
%y = load float addrspace(1)* %gep.1
|
||||
%z = load float addrspace(1)* %gep.2
|
||||
%u = load float addrspace(1)* %gep.3
|
||||
%v = load float addrspace(1)* %gep.4
|
||||
|
||||
%tmp0 = fmul float %u, %v
|
||||
%tmp1 = call float @llvm.fma.f32(float %x, float %y, float %tmp0) #0
|
||||
%tmp2 = fsub float %tmp1, %z
|
||||
|
||||
store float %tmp2, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; fold (fsub x, (fma y, z, (fmul u, v)))
|
||||
; -> (fma (fneg y), z, (fma (fneg u), v, x))
|
||||
|
||||
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_1_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
|
||||
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
||||
|
||||
; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
|
||||
; SI-STD: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
|
||||
|
||||
; SI-DENORM: v_fma_f32 [[TMP0:v[0-9]+]], -[[D]], [[E]], [[A]]
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP0]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-DENORM-SLOWFMAF: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[A]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.4 = getelementptr float addrspace(1)* %gep.0, i32 4
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%x = load float addrspace(1)* %gep.0
|
||||
%y = load float addrspace(1)* %gep.1
|
||||
%z = load float addrspace(1)* %gep.2
|
||||
%u = load float addrspace(1)* %gep.3
|
||||
%v = load float addrspace(1)* %gep.4
|
||||
|
||||
%tmp0 = fmul float %u, %v
|
||||
%tmp1 = call float @llvm.fma.f32(float %y, float %z, float %tmp0) #0
|
||||
%tmp2 = fsub float %x, %tmp1
|
||||
|
||||
store float %tmp2, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
|
||||
|
||||
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_2_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
|
||||
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
||||
|
||||
; SI-STD: v_mad_f32 [[TMP:v[0-9]+]], [[D]], [[E]], -[[C]]
|
||||
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP]]
|
||||
|
||||
; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], [[D]], [[E]], -[[C]]
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]]
|
||||
; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP2]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.4 = getelementptr float addrspace(1)* %gep.0, i32 4
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%x = load float addrspace(1)* %gep.0
|
||||
%y = load float addrspace(1)* %gep.1
|
||||
%z = load float addrspace(1)* %gep.2
|
||||
%u = load float addrspace(1)* %gep.3
|
||||
%v = load float addrspace(1)* %gep.4
|
||||
|
||||
%tmp0 = fmul float %u, %v
|
||||
%tmp1 = call float @llvm.fmuladd.f32(float %x, float %y, float %tmp0) #0
|
||||
%tmp2 = fsub float %tmp1, %z
|
||||
|
||||
store float %tmp2, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
; fold (fsub x, (fmuladd y, z, (fmul u, v)))
|
||||
; -> (fmuladd (fneg y), z, (fmuladd (fneg u), v, x))
|
||||
|
||||
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_3_f32:
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
|
||||
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}}
|
||||
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
||||
|
||||
; SI-STD: v_mad_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
|
||||
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
|
||||
|
||||
; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
|
||||
; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
|
||||
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]]
|
||||
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[C]], [[B]]
|
||||
; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]]
|
||||
; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP2]], [[A]]
|
||||
|
||||
; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI: s_endpgm
|
||||
define void @aggressive_combine_to_mad_fsub_3_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
|
||||
%tid = tail call i32 @llvm.r600.read.tidig.x() #0
|
||||
%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
|
||||
%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
|
||||
%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
|
||||
%gep.3 = getelementptr float addrspace(1)* %gep.0, i32 3
|
||||
%gep.4 = getelementptr float addrspace(1)* %gep.0, i32 4
|
||||
%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
|
||||
|
||||
%x = load float addrspace(1)* %gep.0
|
||||
%y = load float addrspace(1)* %gep.1
|
||||
%z = load float addrspace(1)* %gep.2
|
||||
%u = load float addrspace(1)* %gep.3
|
||||
%v = load float addrspace(1)* %gep.4
|
||||
|
||||
%tmp0 = fmul float %u, %v
|
||||
%tmp1 = call float @llvm.fmuladd.f32(float %y, float %z, float %tmp0) #0
|
||||
%tmp2 = fsub float %x, %tmp1
|
||||
|
||||
store float %tmp2, float addrspace(1)* %gep.out
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone }
|
||||
attributes #1 = { nounwind }
|
||||
Reference in new issue
Block a user