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ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-05 19:42:11 +00:00
parent 40f16cf91d
commit bbc65bbb90
3 changed files with 15 additions and 6 deletions
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12
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -82,8 +82,16 @@ const char *ARMUtils::OpcodeName(unsigned Opcode) {
// FIXME: Auto-gened? // FIXME: Auto-gened?
static unsigned static unsigned
getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) { getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
// For this purpose, we can treat rGPR as if it were GPR. if (RegClassID == ARM::rGPRRegClassID) {
if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID; // Check for The register numbers 13 and 15 that are not permitted for many
// Thumb register specifiers.
if (RawRegister == 13 || RawRegister == 15) {
B->SetErr(-1);
return 0;
}
// For this purpose, we can treat rGPR as if it were GPR.
RegClassID = ARM::GPRRegClassID;
}
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm(). // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
unsigned RegNum = unsigned RegNum =

5
test/MC/Disassembler/ARM/thumb-printf.txt
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@ -26,7 +26,8 @@
# CHECK-NEXT: mov r2, r5 # CHECK-NEXT: mov r2, r5
# CHECK-NEXT: ldr r3, [sp] # CHECK-NEXT: ldr r3, [sp]
# CHECK-NEXT: bl #-8390 # CHECK-NEXT: bl #-8390
# CHECK-NEXT: sub.w sp, r7, #8 # Data bytes (corresponds to an invalid instruction)
# But not: sub.w sp, r7, #8
# CHECK-NEXT: pop.w {r4, r5, r7, lr} # CHECK-NEXT: pop.w {r4, r5, r7, lr}
# CHECK-NEXT: add sp, #16 # CHECK-NEXT: add sp, #16
# CHECK-NEXT: bx lr # CHECK-NEXT: bx lr
@ -63,7 +64,7 @@
0x2a 0x46 0x2a 0x46
0x00 0x9b 0x00 0x9b
0xfd 0xf7 0x9d 0xff 0xfd 0xf7 0x9d 0xff
0xa7 0xf1 0x08 0x0d # 0xa7 0xf1 0x08 0x0d
0xbd 0xe8 0xb0 0x40 0xbd 0xe8 0xb0 0x40
0x04 0xb0 0x04 0xb0
0x70 0x47 0x70 0x47

4
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -42,8 +42,8 @@
# CHECK: ldrd r0, r1, [r7, #64]! # CHECK: ldrd r0, r1, [r7, #64]!
0xf7 0xe9 0x10 0x01 0xf7 0xe9 0x10 0x01
# CHECK: lsls.w r0, pc, #1 # CHECK: lsls.w r0, r5, #1
0x5f 0xea 0x4f 0x00 0x5f 0xea 0x45 0x00
# CHECK: mov r11, r7 # CHECK: mov r11, r7
0xbb 0x46 0xbb 0x46