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Add encoding bits for some Thumb instructions. Plus explicitly set the top two

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bytes of Inst to 0x0000 for the benefit of the Thumb decoder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2009-12-16 02:32:54 +00:00
parent 978b75ee50
commit bbc71b2904
3 changed files with 18 additions and 10 deletions
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19
lib/Target/ARM/ARMInstrFormats.td
View File

@ -920,8 +920,7 @@ class T1Ix2<dag oops, dag iops, InstrItinClass itin,
: Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
class T1JTI<dag oops, dag iops, InstrItinClass itin,
string asm, list<dag> pattern>
: Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>,
Encoding;
: Thumb1I<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
// Two-address instructions
class T1It<dag oops, dag iops, InstrItinClass itin,
@ -986,31 +985,35 @@ class T1pIs<dag oops, dag iops,
InstrItinClass itin, string opc, string asm, list<dag> pattern>
: Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
class Encoding16 : Encoding {
let Inst{31-16} = 0x0000;
}
// A6.2 16-bit Thumb instruction encoding
class T1Encoding<bits<6> opcode> : Encoding {
class T1Encoding<bits<6> opcode> : Encoding16 {
let Inst{15-10} = opcode;
}
// A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
class T1General<bits<5> opcode> : Encoding {
class T1General<bits<5> opcode> : Encoding16 {
let Inst{15-14} = 0b00;
let Inst{13-9} = opcode;
}
// A6.2.2 Data-processing encoding.
class T1DataProcessing<bits<4> opcode> : Encoding {
class T1DataProcessing<bits<4> opcode> : Encoding16 {
let Inst{15-10} = 0b010000;
let Inst{9-6} = opcode;
}
// A6.2.3 Special data instructions and branch and exchange encoding.
class T1Special<bits<4> opcode> : Encoding {
class T1Special<bits<4> opcode> : Encoding16 {
let Inst{15-10} = 0b010001;
let Inst{9-6} = opcode;
}
// A6.2.4 Load/store single data item encoding.
class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding {
class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
let Inst{15-12} = opA;
let Inst{11-9} = opB;
}
@ -1021,7 +1024,7 @@ class T1LdSt2Imm<bits<3> opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes
class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
// A6.2.5 Miscellaneous 16-bit instructions encoding.
class T1Misc<bits<7> opcode> : Encoding {
class T1Misc<bits<7> opcode> : Encoding16 {
let Inst{15-12} = 0b1011;
let Inst{11-5} = opcode;
}

8
lib/Target/ARM/ARMInstrThumb.td
View File

@ -306,7 +306,11 @@ let isBranch = 1, isTerminator = 1 in {
def tBR_JTr : T1JTI<(outs),
(ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
[(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
Encoding16 {
let Inst{15-7} = 0b010001101;
let Inst{2-0} = 0b111;
}
}
}
@ -596,7 +600,7 @@ def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
T1Special<0b1000>;
let Defs = [CPSR] in
def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
"movs\t$dst, $src", []>, Encoding {
"movs\t$dst, $src", []>, Encoding16 {
let Inst{15-6} = 0b0000000000;
}

1
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1911,6 +1911,7 @@ def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
AddrModeNone, Size2Bytes, IIC_iALUx,
"it$mask\t$cc", "", []> {
// 16-bit instruction.
let Inst{31-16} = 0x0000;
let Inst{15-8} = 0b10111111;
}